Lines Matching +full:im +full:-
1 //===- HexagonBitTracker.cpp ----------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
45 // Populate the VRX map (VR to extension-type). in HexagonEvaluator()
47 // P is sign- or zero-extended, locate the virtual register holding that in HexagonEvaluator()
48 // parameter and create an entry in the VRX map indicating the type of ex- in HexagonEvaluator()
50 // This is a bit complicated to do accurately, since the memory layout in- in HexagonEvaluator()
51 // formation is necessary to precisely determine whether an aggregate para- in HexagonEvaluator()
53 // is the association between the physical register that is live-in (i.e. in HexagonEvaluator()
56 // register to a formal parameter from Function (since consecutive live-ins in HexagonEvaluator()
57 // from MRI may not correspond to consecutive formal parameters from Func- in HexagonEvaluator()
58 // tion). To avoid the complications with in-memory arguments, only consi- in HexagonEvaluator()
66 if (ATy->isIntegerTy()) in HexagonEvaluator()
67 Width = ATy->getIntegerBitWidth(); in HexagonEvaluator()
68 else if (ATy->isPointerTy()) in HexagonEvaluator()
101 return IsSubLo ? BT::BitMask(0, RW-1) in mask()
102 : BT::BitMask(RW, 2*RW-1); in mask()
218 // registers. Such parameters can be sign- or zero-extended at the in evaluate()
220 // keeps a list of pairs of live-in physical and virtual registers, in evaluate()
240 // for each instruction, do it here. Global symbols as operands gene- in evaluate()
251 #define im(i) MI.getOperand(i).getImm() in evaluate() macro
259 -> bool { in evaluate()
263 // Get the cell corresponding to the N-th operand. in evaluate()
265 uint16_t W) -> BT::RegisterCell { in evaluate()
276 -> BT::RegisterCell { in evaluate()
282 -> BT::RegisterCell { in evaluate()
285 return eXTR(RC, W-RW, W); in evaluate()
287 // Extract N-th halfword (counting from the least significant position). in evaluate()
289 -> BT::RegisterCell { in evaluate()
295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
309 // Pre-compute the bitwidth here, because it is needed in many cases in evaluate()
323 return rr0(eIMM(im(1), W0), Outputs); in evaluate()
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate()
371 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1)); in evaluate()
379 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs); in evaluate()
381 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate()
385 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3))); in evaluate()
389 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0))); in evaluate()
393 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0)); in evaluate()
394 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); in evaluate()
399 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); in evaluate()
403 RegisterCell M = eMLS(eIMM(im(2), W0), rc(3)); in evaluate()
408 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0)); in evaluate()
418 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3))); in evaluate()
422 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0))); in evaluate()
434 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3))); in evaluate()
440 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs); in evaluate()
446 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs); in evaluate()
448 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate()
452 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3))); in evaluate()
456 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0))); in evaluate()
463 // 32-bit negation is done by "Rd = A2_subri 0, Rs" in evaluate()
482 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0)); in evaluate()
487 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0)); in evaluate()
502 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0)); in evaluate()
506 RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0)); in evaluate()
510 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0)); in evaluate()
528 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs); in evaluate()
536 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate()
540 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3))); in evaluate()
552 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs); in evaluate()
560 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate()
564 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3))); in evaluate()
573 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0))); in evaluate()
577 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0))); in evaluate()
601 return rr0(eASL(rc(1), im(2)), Outputs); in evaluate()
606 return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs); in evaluate()
609 return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs); in evaluate()
612 return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs); in evaluate()
615 return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs); in evaluate()
618 return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs); in evaluate()
626 return rr0(eASR(rc(1), im(2)), Outputs); in evaluate()
631 return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs); in evaluate()
634 return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs); in evaluate()
637 return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs); in evaluate()
640 return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs); in evaluate()
642 // The input is first sign-extended to 64 bits, then the output in evaluate()
646 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1); in evaluate()
650 int64_t S = im(2); in evaluate()
653 // Result: S2_asr_i_r_rnd Rs, u5-1 in evaluate()
655 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1); in evaluate()
666 return rr0(eLSR(rc(1), im(2)), Outputs); in evaluate()
669 return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs); in evaluate()
672 return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs); in evaluate()
675 return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs); in evaluate()
678 return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs); in evaluate()
681 return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs); in evaluate()
685 RC[im(2)] = BT::BitValue::Zero; in evaluate()
690 RC[im(2)] = BT::BitValue::One; in evaluate()
695 uint16_t BX = im(2); in evaluate()
704 uint16_t BX = im(2); in evaluate()
708 .fill(W1+(W1-BX), W0, Zero); in evaluate()
717 uint16_t Wd = im(2), Of = im(3); in evaluate()
723 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1); in evaluate()
726 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1)); in evaluate()
733 uint16_t Wd = im(3), Of = im(4); in evaluate()
737 Wd = W0-Of; in evaluate()
825 // Sign- and zero-extension: in evaluate()
857 // Always produce a 32-bit result. in evaluate()
866 BT::BitValue TV = R1[W1-1]; in evaluate()
953 BT::BitValue V = rc(1)[im(2)]; in evaluate()
979 #undef im in evaluate()
1204 const BT::BitValue &Sign = Res[BitNum-1]; in evaluateLoad()
1232 uint16_t EW = F->second.Width; in evaluateFormalCopy()
1234 // register, and make zero-/sign-extends possible (otherwise we would be ex- in evaluateFormalCopy()
1241 if (F->second.Type == ExtType::SExt) in evaluateFormalCopy()
1243 else if (F->second.Type == ExtType::ZExt) in evaluateFormalCopy()