Lines Matching refs:RS

82     RegisterSet(const RegisterSet &RS) = default;
189 : RS(S), TRI(RI) {} in PrintRegSet()
195 const RegisterSet &RS; member
203 for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) in operator <<()
257 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
957 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) { in isTransparentCopy() argument
958 if (!RD.Reg.isVirtual() || !RS.Reg.isVirtual()) in isTransparentCopy()
965 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1095 bool usedBitsEqual(BitTracker::RegisterRef RD, BitTracker::RegisterRef RS);
1307 BitTracker::RegisterRef RS) { in usedBitsEqual() argument
1309 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in usedBitsEqual()
1315 if (!HBS::getSubregMask(RS, SB, SW, MRI)) in usedBitsEqual()
1357 BitTracker::RegisterRef RS = Op; in processBlock() local
1358 if (!BT.has(RS.Reg)) in processBlock()
1360 if (!HBS::isTransparentCopy(RD, RS, MRI)) in processBlock()
1364 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in processBlock()
1367 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in processBlock()
1368 if (!usedBitsEqual(RD, RS) && !HBS::isEqual(DC, 0, SC, BN, BW)) in processBlock()
1377 .addReg(RS.Reg, 0, RS.Sub); in processBlock()
1709 BitTracker::RegisterRef RS = MI.getOperand(1); in propagateRegCopy() local
1710 if (!HBS::isTransparentCopy(RD, RS, MRI)) in propagateRegCopy()
1712 if (RS.Sub != 0) in propagateRegCopy()
1713 Changed = HBS::replaceRegWithSub(RD.Reg, RS.Reg, RS.Sub, MRI); in propagateRegCopy()
1715 Changed = HBS::replaceReg(RD.Reg, RS.Reg, MRI); in propagateRegCopy()
1744 BitTracker::RegisterRef RS = MI.getOperand(SrcX); in propagateRegCopy() local
1745 Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI); in propagateRegCopy()
1955 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf() local
1956 if (!BT.has(RS.Reg)) in genStoreUpperHalf()
1958 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreUpperHalf()
1960 unsigned B = (RS.Sub == Hexagon::isub_hi) ? 32 : 0; in genStoreUpperHalf()
2001 BitTracker::RegisterRef RS = MI->getOperand(2); in genStoreImmediate() local
2002 if (!BT.has(RS.Reg)) in genStoreImmediate()
2004 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreImmediate()
2179 BitTracker::RegisterRef RS = Op; in genExtractLow() local
2180 if (!BT.has(RS.Reg)) in genExtractLow()
2182 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in genExtractLow()
2184 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in genExtractLow()
2188 if (!validateReg(RS, NewOpc, 1)) in genExtractLow()
2195 .addReg(RS.Reg, 0, RS.Sub); in genExtractLow()
2367 BitTracker::RegisterRef RS = MI->getOperand(1); in simplifyTstbit() local
2370 if (!BT.has(RS.Reg) || !HBS::getSubregMask(RS, F, W, MRI)) in simplifyTstbit()
2376 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in simplifyTstbit()
2378 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg != RS.Reg) { in simplifyTstbit()