Lines Matching refs:NewR

237     static bool replaceReg(Register OldR, Register NewR,
241 static bool replaceRegWithSub(Register OldR, Register NewR, unsigned NewSR,
243 static bool replaceSubWithSub(Register OldR, unsigned OldSR, Register NewR,
383 bool HexagonBitSimplify::replaceReg(Register OldR, Register NewR, in replaceReg() argument
385 if (!OldR.isVirtual() || !NewR.isVirtual()) in replaceReg()
391 I->setReg(NewR); in replaceReg()
396 bool HexagonBitSimplify::replaceRegWithSub(Register OldR, Register NewR, in replaceRegWithSub() argument
399 if (!OldR.isVirtual() || !NewR.isVirtual()) in replaceRegWithSub()
407 I->setReg(NewR); in replaceRegWithSub()
414 Register NewR, unsigned NewSR, in replaceSubWithSub() argument
416 if (!OldR.isVirtual() || !NewR.isVirtual()) in replaceSubWithSub()
426 I->setReg(NewR); in replaceSubWithSub()
1374 Register NewR = MRI.createVirtualRegister(FRC); in processBlock() local
1376 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR) in processBlock()
1378 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in processBlock()
1645 Register NewR = MRI.createVirtualRegister(FRC); in processBlock() local
1646 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR) in processBlock()
1648 BT.put(BitTracker::RegisterRef(NewR), BT.get(MR)); in processBlock()
1649 HBS::replaceReg(R, NewR, MRI); in processBlock()
1664 Register NewR = MRI.createVirtualRegister(FRC); in processBlock() local
1665 BuildMI(B, At, DL, HII.get(TargetOpcode::REG_SEQUENCE), NewR) in processBlock()
1670 BT.put(BitTracker::RegisterRef(NewR), BT.get(R)); in processBlock()
1671 HBS::replaceReg(R, NewR, MRI); in processBlock()
2062 Register NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass); in genPackhl() local
2066 BuildMI(B, At, DL, HII.get(Hexagon::S2_packhl), NewR) in genPackhl()
2069 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genPackhl()
2070 BT.put(BitTracker::RegisterRef(NewR), RC); in genPackhl()
2089 unsigned NewR = 0; in genExtractHalf() local
2094 NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractHalf()
2095 BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR) in genExtractHalf()
2100 NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractHalf()
2101 BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR) in genExtractHalf()
2106 if (NewR == 0) in genExtractHalf()
2108 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractHalf()
2109 BT.put(BitTracker::RegisterRef(NewR), RC); in genExtractHalf()
2134 Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genCombineHalf() local
2137 BuildMI(B, At, DL, HII.get(COpc), NewR) in genCombineHalf()
2140 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genCombineHalf()
2141 BT.put(BitTracker::RegisterRef(NewR), RC); in genCombineHalf()
2191 Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractLow() local
2194 auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR) in genExtractLow()
2200 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractLow()
2201 BT.put(BitTracker::RegisterRef(NewR), RC); in genExtractLow()
2313 unsigned NewR = 0; in genBitSplit() local
2331 NewR = Op0.getReg(); in genBitSplit()
2334 if (!NewR) { in genBitSplit()
2335 NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass); in genBitSplit()
2336 auto NewBS = BuildMI(B, At, DL, HII.get(Hexagon::A4_bitspliti), NewR) in genBitSplit()
2342 HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_lo, MRI); in genBitSplit()
2343 HBS::replaceRegWithSub(S, NewR, Hexagon::isub_hi, MRI); in genBitSplit()
2345 HBS::replaceRegWithSub(S, NewR, Hexagon::isub_lo, MRI); in genBitSplit()
2346 HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_hi, MRI); in genBitSplit()
2396 Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in simplifyTstbit() local
2397 BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR) in simplifyTstbit()
2400 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyTstbit()
2401 BT.put(NewR, RC); in simplifyTstbit()
2405 Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in simplifyTstbit() local
2407 BuildMI(B, At, DL, HII.get(NewOpc), NewR); in simplifyTstbit()
2408 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyTstbit()
2578 Register NewR = MRI.createVirtualRegister(FRC); in simplifyExtractLow() local
2581 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2603 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyExtractLow()
2604 BT.put(BitTracker::RegisterRef(NewR), RC); in simplifyExtractLow()
2650 Register NewR = MRI.createVirtualRegister(FRC); in simplifyRCmp0() local
2651 BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), NewR) in simplifyRCmp0()
2653 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyRCmp0()
2659 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
2715 Register NewR = MRI.createVirtualRegister(FRC); in simplifyRCmp0() local
2716 BuildMI(B, At, DL, HII.get(Hexagon::C2_muxii), NewR) in simplifyRCmp0()
2720 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyRCmp0()
2725 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()