Lines Matching +full:upper +full:- +full:cal
1 //===- HexagonBitSimplify.cpp ---------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
52 static cl::opt<bool> PreserveTiedOps("hexbit-keep-tied", cl::Hidden,
54 static cl::opt<bool> GenExtract("hexbit-extract", cl::Hidden,
56 static cl::opt<bool> GenBitSplit("hexbit-bitsplit", cl::Hidden,
59 static cl::opt<unsigned> MaxExtract("hexbit-max-extract", cl::Hidden,
62 static cl::opt<unsigned> MaxBitSplit("hexbit-max-bitsplit", cl::Hidden,
66 static cl::opt<unsigned> RegisterSetLimit("hexbit-registerset-limit",
162 // A.test(B) <=> A-B != {} in includes()
270 // the function top-down or bottom-up via the dominator tree, and keep
286 INITIALIZE_PASS_BEGIN(HexagonBitSimplify, "hexagon-bit-simplify",
289 INITIALIZE_PASS_END(HexagonBitSimplify, "hexagon-bit-simplify", in INITIALIZE_PASS_DEPENDENCY()
305 for (auto *DTN : children<MachineDomTreeNode*>(MDT->getNode(&B))) in INITIALIZE_PASS_DEPENDENCY()
306 Changed |= visitBlock(*(DTN->getBlock()), T, NewAVs); in INITIALIZE_PASS_DEPENDENCY()
371 for (uint16_t i = B+W; i > B; --i) { in getConst()
372 const BitTracker::BitValue &BV = RC[i-1]; in getConst()
391 I->setReg(NewR); in replaceReg()
407 I->setReg(NewR); in replaceRegWithSub()
408 I->setSubReg(NewSR); in replaceRegWithSub()
424 if (I->getSubReg() != OldSR) in replaceSubWithSub()
426 I->setReg(NewR); in replaceSubWithSub()
427 I->setSubReg(NewSR); in replaceSubWithSub()
440 Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC); in getSubregMask()
446 switch (RC->getID()) { in getSubregMask()
449 Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2; in getSubregMask()
486 // All stores (except 64-bit stores) take a 32-bit register as the source
657 if (OpN == D.getNumOperands()-1) in getUsedBits()
663 // One register source. Used bits: R1[0-7]. in getUsedBits()
675 // One register source. Used bits: R1[0-15]. in getUsedBits()
688 // One register source. Used bits: R1[16-31]. in getUsedBits()
696 // Two register sources. Used bits: R1[0-7], R2[0-7]. in getUsedBits()
706 // Two register sources. Used bits: R1[0-15], R2[0-15]. in getUsedBits()
761 // Two register sources. Used bits: R1[0-15], R2[16-31]. in getUsedBits()
818 // Two register sources, used bits: R1[16-31], R2[0-15]. in getUsedBits()
870 // Two register sources, used bits: R1[16-31], R2[16-31]. in getUsedBits()
935 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass()
941 switch (RC->getID()) { in getFinalVRegClass()
954 // register, but a 64-bit register with a subregister can be replaced
955 // with a 32-bit register.
973 [NewSub] (const MachineOperand &Op) -> bool { in hasTiedUse()
1005 if (UseI->isDebugInstr()) in isDead()
1007 if (UseI->isPHI()) { in isDead()
1008 assert(!UseI->getOperand(0).getSubReg()); in isDead()
1009 Register DR = UseI->getOperand(0).getReg(); in isDead()
1024 MachineBasicBlock *B = N->getBlock(); in runOnNode()
1030 unsigned Opc = MI->getOpcode(); in runOnNode()
1031 // Do not touch lifetime markers. This is why the target-independent DCE in runOnNode()
1037 if (MI->isInlineAsm()) in runOnNode()
1040 if (!MI->isPHI() && !MI->isSafeToMove(nullptr, Store)) in runOnNode()
1045 for (auto &Op : MI->operands()) { in runOnNode()
1058 B->erase(MI); in runOnNode()
1073 // that define a single register (unlike post-increment loads, for example).
1160 LostB = Width-S; in isLossyShiftLeft()
1229 // The vector Bits has the same size, as the size of Reg in bits. If the cal-
1230 // culation fails (i.e. the used bits are unknown), it returns false. Other-
1248 MachineInstr &UseI = *I->getParent(); in computeUsedBits()
1269 // The register in question may be used with a sub-register, whereas Bits
1271 // argument Begin indicates where in Bits is the lowest-significant bit
1274 // the operand 1 is a 32-bit register, which happens to be a subregister
1275 // of the 64-bit register %2, and that subregister starts at position 32.
1276 // In this case Begin=32, since Bits[32] would be the lowest-significant bit
1339 if (MI->getOpcode() == TargetOpcode::COPY) in processBlock()
1341 if (MI->isPHI() || MI->hasUnmodeledSideEffects() || MI->isInlineAsm()) in processBlock()
1343 unsigned NumD = MI->getDesc().getNumDefs(); in processBlock()
1347 BitTracker::RegisterRef RD = MI->getOperand(0); in processBlock()
1354 for (auto &Op : MI->uses()) { in processBlock()
1372 const DebugLoc &DL = MI->getDebugLoc(); in processBlock()
1384 // %3 = copy %2 ; <- inserted in processBlock()
1385 // ... = %3 ; <- replaced from %2 in processBlock()
1399 // Recognize instructions that produce constant values known at compile-time.
1438 // Generate a transfer-immediate instruction that is appropriate for the
1468 auto &HST = MF->getSubtarget<HexagonSubtarget>(); in genTfrConst()
1472 MF->getFunction().hasOptSize()) { in genTfrConst()
1514 DebugLoc DL = I->getDebugLoc(); in processBlock()
1515 auto At = I->isPHI() ? B.getFirstNonPHI() : I; in processBlock()
1599 // Check if there is a super-register, whose part (with a subregister) in findMatch()
1632 unsigned Opc = I->getOpcode(); in processBlock()
1637 DebugLoc DL = I->getDebugLoc(); in processBlock()
1638 auto At = I->isPHI() ? B.getFirstNonPHI() : I; in processBlock()
1759 unsigned Opc = I->getOpcode(); in processBlock()
1836 // Match 16-bit chunks, where the RC[B..B+15] references exactly one in matchHalf()
1838 // This is meant to match "v1[0-15]", where v1 = { [0]:0 [1-15]:v1... }, in matchHalf()
1839 // and RC = { [0]:0 [1-15]:v1[1-15]... }. in matchHalf()
1848 unsigned P = RC[I].RefI.Pos; // The RefI.Pos will be advanced by I-B. in matchHalf()
1849 if (P < I-B) in matchHalf()
1851 unsigned Pos = P - (I-B); in matchHalf()
1913 return OpRC->hasSubClassEq(RRC); in validateReg()
1946 // If MI stores the upper halfword of a register (potentially obtained via
1950 unsigned Opc = MI->getOpcode(); in genStoreUpperHalf()
1954 MachineOperand &ValOp = MI->getOperand(2); in genStoreUpperHalf()
1965 MI->setDesc(HII.get(Hexagon::S2_storerf_io)); in genStoreUpperHalf()
1971 // If MI stores a value known at compile-time, and the value is within a range
1972 // that avoids using constant-extenders, replace it with a store-immediate.
1974 unsigned Opc = MI->getOpcode(); in genStoreImmediate()
1989 // Avoid stores to frame-indices (due to an unknown offset). in genStoreImmediate()
1990 if (!MI->getOperand(0).isReg()) in genStoreImmediate()
1992 MachineOperand &OffOp = MI->getOperand(1); in genStoreImmediate()
1998 if (!isUIntN(6+Align, Off) || (Off & ((1<<Align)-1))) in genStoreImmediate()
2001 BitTracker::RegisterRef RS = MI->getOperand(2); in genStoreImmediate()
2009 // Only consider 8-bit values to avoid constant-extenders. in genStoreImmediate()
2023 // This silences a -Wuninitialized false positive on GCC 5.4. in genStoreImmediate()
2029 MI->removeOperand(2); in genStoreImmediate()
2032 MI->setDesc(HII.get(Hexagon::S4_storeirb_io)); in genStoreImmediate()
2035 MI->setDesc(HII.get(Hexagon::S4_storeirh_io)); in genStoreImmediate()
2038 MI->setDesc(HII.get(Hexagon::S4_storeiri_io)); in genStoreImmediate()
2041 MI->addOperand(MachineOperand::CreateImm(V)); in genStoreImmediate()
2047 // the pack-halfwords. The intent is to cause the entire sequence to become
2051 unsigned Opc = MI->getOpcode(); in genPackhl()
2061 MachineBasicBlock &B = *MI->getParent(); in genPackhl()
2063 DebugLoc DL = MI->getDebugLoc(); in genPackhl()
2064 auto At = MI->isPHI() ? B.getFirstNonPHI() in genPackhl()
2075 // replace it with zero-extend or extractu.
2083 unsigned Opc = MI->getOpcode(); in genExtractHalf()
2084 MachineBasicBlock &B = *MI->getParent(); in genExtractHalf()
2085 DebugLoc DL = MI->getDebugLoc(); in genExtractHalf()
2090 auto At = MI->isPHI() ? B.getFirstNonPHI() in genExtractHalf()
2125 unsigned Opc = MI->getOpcode(); in genCombineHalf()
2132 MachineBasicBlock &B = *MI->getParent(); in genCombineHalf()
2133 DebugLoc DL = MI->getDebugLoc(); in genCombineHalf()
2135 auto At = MI->isPHI() ? B.getFirstNonPHI() in genCombineHalf()
2146 // with zero-extend byte/half, and-immediate, or extractu, as appropriate.
2149 unsigned Opc = MI->getOpcode(); in genExtractLow()
2156 if (Opc == Hexagon::A2_andir && MI->getOperand(2).isImm()) { in genExtractLow()
2157 int32_t Imm = MI->getOperand(2).getImm(); in genExtractLow()
2162 if (MI->hasUnmodeledSideEffects() || MI->isInlineAsm()) in genExtractLow()
2165 while (W > 0 && RC[W-1].is(0)) in genExtractLow()
2166 W--; in genExtractLow()
2173 MachineBasicBlock &B = *MI->getParent(); in genExtractLow()
2174 DebugLoc DL = MI->getDebugLoc(); in genExtractLow()
2176 for (auto &Op : MI->uses()) { in genExtractLow()
2192 auto At = MI->isPHI() ? B.getFirstNonPHI() in genExtractLow()
2197 MIB.addImm((1 << W) - 1); in genExtractLow()
2217 unsigned Opc = MI->getOpcode(); in genBitSplit()
2228 auto ctlz = [] (const BitTracker::RegisterCell &C) -> unsigned { in genBitSplit()
2230 while (Z > 0 && C[Z-1].is(0)) in genBitSplit()
2231 --Z; in genBitSplit()
2232 return C.width() - Z; in genBitSplit()
2241 // is fully unknown, and that all its bits are self-references. in genBitSplit()
2250 // All the non-zero bits should be consecutive bits from the same register. in genBitSplit()
2251 for (unsigned i = 1; i < W-Z; ++i) { in genBitSplit()
2262 // non-zeros in RC. in genBitSplit()
2263 unsigned SRC = MRI.getRegClass(S)->getID(); in genBitSplit()
2270 if (SC.width() != W || ctlz(SC) != W-Z) in genBitSplit()
2278 if (Pos <= P && (Pos + W-Z) != P) in genBitSplit()
2302 DebugLoc DL = DefS->getDebugLoc(); in genBitSplit()
2303 MachineBasicBlock &B = *DefS->getParent(); in genBitSplit()
2304 auto At = DefS->isPHI() ? B.getFirstNonPHI() in genBitSplit()
2306 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID) in genBitSplit()
2310 unsigned ImmOp = Pos <= P ? W-Z : Z; in genBitSplit()
2315 if (In->getOpcode() != Hexagon::A4_bitspliti) in genBitSplit()
2317 MachineOperand &Op1 = In->getOperand(1); in genBitSplit()
2320 if (In->getOperand(2).getImm() != ImmOp) in genBitSplit()
2323 MachineOperand &Op0 = In->getOperand(0); in genBitSplit()
2362 unsigned Opc = MI->getOpcode(); in simplifyTstbit()
2366 unsigned BN = MI->getOperand(2).getImm(); in simplifyTstbit()
2367 BitTracker::RegisterRef RS = MI->getOperand(1); in simplifyTstbit()
2369 DebugLoc DL = MI->getDebugLoc(); in simplifyTstbit()
2372 MachineBasicBlock &B = *MI->getParent(); in simplifyTstbit()
2373 auto At = MI->isPHI() ? B.getFirstNonPHI() in simplifyTstbit()
2380 // Need to map V.RefI.Reg to a 32-bit register, i.e. if it is in simplifyTstbit()
2389 P -= 32; in simplifyTstbit()
2415 // Detect whether RD is a bitfield extract (sign- or zero-extended) of
2436 // The code is mostly class-independent, except for the part that generates in simplifyExtractLow()
2449 // The same logic applies to sign-extended fields. in simplifyExtractLow()
2454 const BitTracker::BitValue &TopV = RC[W-1]; in simplifyExtractLow()
2456 // Eliminate candidates that have self-referential bits, since they in simplifyExtractLow()
2458 // have compile-time constant values. in simplifyExtractLow()
2471 for (--W; W > 0 && RC[W-1].is(S); --W) in simplifyExtractLow()
2479 // This could still be a sign-extended extract. in simplifyExtractLow()
2481 if (TopV.RefI.Reg == RD.Reg || TopV.RefI.Pos == W-1) in simplifyExtractLow()
2483 for (--W; W > 0 && RC[W-1] == TopV; --W) in simplifyExtractLow()
2500 << (Signed ? "sign" : "zero") << "-extended\n"; in simplifyExtractLow()
2522 while (Off <= SW-Len) { in simplifyExtractLow()
2539 if (Off > SW-Len) in simplifyExtractLow()
2569 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2571 const MachineOperand &SrcOp = MI->getOperand(1); in simplifyExtractLow()
2576 DebugLoc DL = MI->getDebugLoc(); in simplifyExtractLow()
2577 MachineBasicBlock &B = *MI->getParent(); in simplifyExtractLow()
2579 auto At = MI->isPHI() ? B.getFirstNonPHI() in simplifyExtractLow()
2590 MIB.addImm((1u << Len) - 1); in simplifyExtractLow()
2614 unsigned Opc = MI->getOpcode(); in simplifyRCmp0()
2617 MachineOperand &CmpOp = MI->getOperand(2); in simplifyRCmp0()
2626 MachineBasicBlock &B = *MI->getParent(); in simplifyRCmp0()
2627 const DebugLoc &DL = MI->getDebugLoc(); in simplifyRCmp0()
2628 auto At = MI->isPHI() ? B.getFirstNonPHI() in simplifyRCmp0()
2633 BitTracker::RegisterRef SR = MI->getOperand(1); in simplifyRCmp0()
2669 return !Op.getCImm()->isZero(); in simplifyRCmp0()
2671 return !Op.getFPImm()->isZero(); in simplifyRCmp0()
2681 return Op.getCImm()->isZero(); in simplifyRCmp0()
2683 return Op.getFPImm()->isZero(); in simplifyRCmp0()
2687 // If the source register is known to be 0 or non-0, the comparison can in simplifyRCmp0()
2690 assert(KnownZ != KnownNZ && "Register cannot be both 0 and non-0"); in simplifyRCmp0()
2699 if (SR.Sub == 0 && InpDef->getOpcode() == Hexagon::C2_muxii) { in simplifyRCmp0()
2700 MachineOperand &Src1 = InpDef->getOperand(2); in simplifyRCmp0()
2701 MachineOperand &Src2 = InpDef->getOperand(3); in simplifyRCmp0()
2702 // Check if both are non-zero. in simplifyRCmp0()
2711 // If for both operands we know that they are either 0 or non-0, in simplifyRCmp0()
2717 .addReg(InpDef->getOperand(1).getReg()) in simplifyRCmp0()
2746 unsigned Opc = MI->getOpcode(); in processBlock()
2750 if (MI->mayStore()) { in processBlock()
2759 const MachineOperand &Op0 = MI->getOperand(0); in processBlock()
2768 if (FRC->getID() == Hexagon::DoubleRegsRegClassID) { in processBlock()
2775 if (FRC->getID() == Hexagon::IntRegsRegClassID) { in processBlock()
2786 if (FRC->getID() == Hexagon::PredRegsRegClassID) { in processBlock()
2976 INITIALIZE_PASS(HexagonLoopRescheduling, "hexagon-loop-resched",
3004 if (!BTP->has(Reg)) in isConst()
3006 const BitTracker::RegisterCell &RC = BTP->lookup(Reg); in isConst()
3017 unsigned Opc = MI->getOpcode(); in isBitShuffle()
3047 for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) { in isStoreInput()
3048 const MachineOperand &Op = MI->getOperand(i); in isStoreInput()
3052 return i == n-1; in isStoreInput()
3058 if (!BTP->has(OutR) || !BTP->has(InpR)) in isShuffleOf()
3060 const BitTracker::RegisterCell &OutC = BTP->lookup(OutR); in isShuffleOf()
3073 if (!BTP->has(OutR1) || !BTP->has(InpR1) || !BTP->has(OutR2)) in isSameShuffle()
3075 const BitTracker::RegisterCell &OutC1 = BTP->lookup(OutR1); in isSameShuffle()
3076 const BitTracker::RegisterCell &OutC2 = BTP->lookup(OutR2); in isSameShuffle()
3107 const TargetRegisterClass *PhiRC = MRI->getRegClass(NewPredR); in moveGroup()
3108 Register PhiR = MRI->createVirtualRegister(PhiRC); in moveGroup()
3109 BuildMI(LB, At, At->getDebugLoc(), HII->get(TargetOpcode::PHI), PhiR) in moveGroup()
3118 const TargetRegisterClass *RC = MRI->getRegClass(DR); in moveGroup()
3119 Register NewDR = MRI->createVirtualRegister(RC); in moveGroup()
3120 DebugLoc DL = SI->getDebugLoc(); in moveGroup()
3122 auto MIB = BuildMI(LB, At, DL, HII->get(SI->getOpcode()), NewDR); in moveGroup()
3123 for (const MachineOperand &Op : SI->operands()) { in moveGroup()
3150 for (const MachineOperand &MO : MRI->use_operands(PR)) { in processLoop()
3152 if (UseI->getParent() != C.LB) { in processLoop()
3169 << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() in processLoop()
3171 << I.LB->getNumber() << ')'; in processLoop()
3184 // the output of the loop cannot be used in a non-shuffling instruction in processLoop()
3203 for (auto UI = MRI->use_begin(DefR), UE = MRI->use_end(); UI != UE; ++UI) { in processLoop()
3204 MachineInstr *UseI = UI->getParent(); in processLoop()
3205 if (UseI->getParent() == C.LB) { in processLoop()
3206 if (UseI->isPHI()) { in processLoop()
3210 if (UseI->getOperand(Idx+1).getMBB() != C.LB) in processLoop()
3218 // suitable for a copy-out. in processLoop()
3238 // the loop-carried register (through a phi node) instead of the (currently in processLoop()
3239 // loop-carried) output register. in processLoop()
3275 auto LoopInpEq = [G] (const PhiInfo &P) -> bool { in processLoop()
3299 auto LoopInpEq = [G] (const PhiInfo &P) -> bool { in processLoop()
3306 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PrehR)) { in processLoop()
3307 const MachineInstr *DefPrehR = MRI->getVRegDef(F->PR.Reg); in processLoop()
3308 unsigned Opc = DefPrehR->getOpcode(); in processLoop()
3311 if (!DefPrehR->getOperand(1).isImm()) in processLoop()
3313 if (DefPrehR->getOperand(1).getImm() != 0) in processLoop()
3315 const TargetRegisterClass *RC = MRI->getRegClass(G.Inp.Reg); in processLoop()
3316 if (RC != MRI->getRegClass(F->PR.Reg)) { in processLoop()
3317 PrehR = MRI->createVirtualRegister(RC); in processLoop()
3320 auto T = C.PB->getFirstTerminator(); in processLoop()
3321 DebugLoc DL = (T != C.PB->end()) ? T->getDebugLoc() : DebugLoc(); in processLoop()
3322 BuildMI(*C.PB, T, DL, HII->get(TfrI), PrehR) in processLoop()
3325 PrehR = F->PR.Reg; in processLoop()
3330 // it would match for the input being a 32-bit register, and PrehR in processLoop()
3331 // being a 64-bit register (where the low 32 bits match). This could in processLoop()
3333 if (MRI->getRegClass(PrehR) != MRI->getRegClass(G.Inp.Reg)) in processLoop()
3335 moveGroup(G, *F->LB, *F->PB, F->LB->getFirstNonPHI(), F->DefR, PrehR); in processLoop()
3377 // edge from B to EP is non-critical. in runOnMachineFunction()
3378 if (Succ->pred_size() == 1) in runOnMachineFunction()
3393 //===----------------------------------------------------------------------===//
3395 //===----------------------------------------------------------------------===//