1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
13 //===----------------------------------------------------------------------===//
65 #define DEBUG_TYPE "asm-printer"
71   unsigned Pair = *RI->superregs(Reg).begin();  in getHexagonRegisterPair()
78   const MachineOperand &MO = MI->getOperand(OpNo);  in printOperand()
90     MO.getMBB()->getSymbol()->print(O, MAI);  in printOperand()
93     GetCPISymbol(MO.getIndex())->print(O, MAI);  in printOperand()
101 // isBlockOnlyReachableByFallthrough - We need to override this since the
109   if (MBB->hasAddressTaken())  in isBlockOnlyReachableByFallthrough()
114 /// PrintAsmOperand - Print out an operand for an inline asm expression.
128     case 'H': { // The highest-numbered register of a pair.  in PrintAsmOperand()
129       const MachineOperand &MO = MI->getOperand(OpNo);  in PrintAsmOperand()
130       const MachineFunction &MF = *MI->getParent()->getParent();  in PrintAsmOperand()
137         RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?  in PrintAsmOperand()
146       if (MI->getOperand(OpNo).isImm())  in PrintAsmOperand()
163   const MachineOperand &Base  = MI->getOperand(OpNo);  in PrintAsmMemoryOperand()
164   const MachineOperand &Offset = MI->getOperand(OpNo+1);  in PrintAsmMemoryOperand()
186   if (Imm.getExpr()->evaluateAsAbsolute(Value)) {  in smallData()
209     if (Sym->isUndefined()) {  in smallData()
229     StringRef SymbolName = MOSymbol->getName();  in smallData()
237     if (Sym->isUndefined()) {  in smallData()
258     int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();  in ScaleVectorOffset()
269   const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();  in HexagonProcessInstruction()
270   const MachineFunction &MF = *MI.getParent()->getParent();  in HexagonProcessInstruction()
328     if (!OutStreamer->hasRawTextSupport()) {  in HexagonProcessInstruction()
330       MCSectionSubPair Current = OutStreamer->getCurrentSection();  in HexagonProcessInstruction()
335       OutStreamer->switchSection(Current.first, Current.second);  in HexagonProcessInstruction()
347     if (!OutStreamer->hasRawTextSupport()) {  in HexagonProcessInstruction()
349       MCSectionSubPair Current = OutStreamer->getCurrentSection();  in HexagonProcessInstruction()
352       OutStreamer->switchSection(Current.first, Current.second);  in HexagonProcessInstruction()
373   // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo  in HexagonProcessInstruction()
377     MCOperand &Rt = Inst.getOperand(3);  in HexagonProcessInstruction()  local
378     assert(Rt.isReg() && "Expected register and none was found");  in HexagonProcessInstruction()
379     unsigned Reg = RI->getEncodingValue(Rt.getReg());  in HexagonProcessInstruction()
384     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));  in HexagonProcessInstruction()
388     MCOperand &Rt = Inst.getOperand(2);  in HexagonProcessInstruction()  local
389     assert(Rt.isReg() && "Expected register and none was found");  in HexagonProcessInstruction()
390     unsigned Reg = RI->getEncodingValue(Rt.getReg());  in HexagonProcessInstruction()
395     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));  in HexagonProcessInstruction()
400     MCOperand &Rt = Inst.getOperand(2);  in HexagonProcessInstruction()  local
401     assert(Rt.isReg() && "Expected register and none was found");  in HexagonProcessInstruction()
402     unsigned Reg = RI->getEncodingValue(Rt.getReg());  in HexagonProcessInstruction()
407     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));  in HexagonProcessInstruction()
414     unsigned Reg = RI->getEncodingValue(Rs.getReg());  in HexagonProcessInstruction()
415     if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2  in HexagonProcessInstruction()
431     bool Success = Expr->evaluateAsAbsolute(Imm);  in HexagonProcessInstruction()
458     bool Success = Expr->evaluateAsAbsolute(Imm);  in HexagonProcessInstruction()
466       unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);  in HexagonProcessInstruction()
467       unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);  in HexagonProcessInstruction()
489   // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd  in HexagonProcessInstruction()
494     bool Success = Expr->evaluateAsAbsolute(Imm);  in HexagonProcessInstruction()
516   // Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"  in HexagonProcessInstruction()
525     bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);  in HexagonProcessInstruction()
527       const MCExpr *MOne = MCConstantExpr::create(-1, OutContext);  in HexagonProcessInstruction()
540   // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"  in HexagonProcessInstruction()
543     unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);  in HexagonProcessInstruction()
544     unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);  in HexagonProcessInstruction()
555     unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);  in HexagonProcessInstruction()
556     unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);  in HexagonProcessInstruction()
569     unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);  in HexagonProcessInstruction()
570     unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);  in HexagonProcessInstruction()
584     bool Success = Expr->evaluateAsAbsolute(Value);  in HexagonProcessInstruction()
587     if (Value < 0 && Value > -256) {  in HexagonProcessInstruction()
597     MCOperand &Rt = Inst.getOperand(1);  in HexagonProcessInstruction()  local
598     assert(Rt.isReg() && "Expected register and none was found");  in HexagonProcessInstruction()
599     unsigned Reg = RI->getEncodingValue(Rt.getReg());  in HexagonProcessInstruction()
604     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));  in HexagonProcessInstruction()
747   Hexagon_MC::verifyInstructionPredicates(MI->getOpcode(),  in emitInstruction()
753   const MCInstrInfo &MCII = *Subtarget->getInstrInfo();  in emitInstruction()
755   if (MI->isBundle()) {  in emitInstruction()
756     const MachineBasicBlock* MBB = MI->getParent();  in emitInstruction()
757     MachineBasicBlock::const_instr_iterator MII = MI->getIterator();  in emitInstruction()  local
759     for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)  in emitInstruction()
760       if (!MII->isDebugInstr() && !MII->isImplicitDef())  in emitInstruction()
761         HexagonLowerToMC(MCII, &*MII, MCB, *this);  in emitInstruction()
766   const MachineFunction &MF = *MI->getParent()->getParent();  in emitInstruction()
768   if (MI->isBundle() && HII.getBundleNoShuf(*MI))  in emitInstruction()
771   MCContext &Ctx = OutStreamer->getContext();  in emitInstruction()
777   OutStreamer->emitInstruction(MCB, getSubtargetInfo());  in emitInstruction()
787       static_cast<HexagonTargetStreamer &>(*OutStreamer->getTargetStreamer());  in emitEndOfAsmFile()
794       static_cast<HexagonTargetStreamer &>(*OutStreamer->getTargetStreamer());  in emitAttributes()
815   // { 	immext(#...) // upper 26-bits of trampoline  in EmitSled()
816   //    r6 = ##...   // lower  6-bits of trampoline  in EmitSled()
817   //    immext(#...) // upper 26-bits of func id  in EmitSled()
823   OutStreamer->emitLabel(CurSled);  in EmitSled()
826   SledJump->setOpcode(Hexagon::J2_jump);  in EmitSled()
828   SledJump->addOperand(MCOperand::createExpr(HexagonMCExpr::create(  in EmitSled()
840   // special-case this and combine them into a single packet.  in EmitSled()
843   OutStreamer->emitLabel(PostSled);  in EmitSled()