Lines Matching refs:Decoder

110                                            const MCDisassembler *Decoder) {  in DecodeGPRRegisterClass()  argument
120 const MCDisassembler *Decoder) { in DecodeFPR32RegisterClass() argument
130 const MCDisassembler *Decoder) { in DecodesFPR32RegisterClass() argument
140 const MCDisassembler *Decoder) { in DecodesFPR64RegisterClass() argument
150 const MCDisassembler *Decoder) { in DecodesFPR64_VRegisterClass() argument
160 const MCDisassembler *Decoder) { in DecodeFPR64RegisterClass() argument
172 const MCDisassembler *Decoder) { in DecodesFPR128RegisterClass() argument
182 const MCDisassembler *Decoder) { in DecodesGPRRegisterClass() argument
192 const MCDisassembler *Decoder) { in DecodemGPRRegisterClass() argument
204 const MCDisassembler *Decoder) { in DecodeGPRSPRegisterClass() argument
214 const MCDisassembler *Decoder) { in DecodeGPRPairRegisterClass() argument
216 Decoder->getSubtargetInfo().getFeatureBits(); in DecodeGPRPairRegisterClass()
229 const MCDisassembler *Decoder) { in decodeUImmOperand() argument
238 const MCDisassembler *Decoder) { in decodeOImmOperand() argument
245 const MCDisassembler *Decoder) { in decodeLRW16Imm8() argument
259 const MCDisassembler *Decoder) { in decodeJMPIXImmOperand() argument
278 const MCDisassembler *Decoder) { in DecodeRegSeqOperand() argument
284 if (DecodeGPRRegisterClass(Inst, Ry, Address, Decoder) == in DecodeRegSeqOperand()
295 const MCDisassembler *Decoder) { in DecodeRegSeqOperandF1() argument
301 if (DecodesFPR32RegisterClass(Inst, Ry, Address, Decoder) == in DecodeRegSeqOperandF1()
312 const MCDisassembler *Decoder) { in DecodeRegSeqOperandD1() argument
318 if (DecodesFPR64RegisterClass(Inst, Ry, Address, Decoder) == in DecodeRegSeqOperandD1()
329 const MCDisassembler *Decoder) { in DecodeRegSeqOperandF2() argument
335 if (DecodeFPR32RegisterClass(Inst, Ry, Address, Decoder) == in DecodeRegSeqOperandF2()
346 const MCDisassembler *Decoder) { in DecodeRegSeqOperandD2() argument
352 if (DecodeFPR64RegisterClass(Inst, Ry, Address, Decoder) == in DecodeRegSeqOperandD2()
363 const MCDisassembler *Decoder) { in decodeImmShiftOpValue() argument
371 const MCDisassembler *Decoder) { in decodeSImmOperand() argument