Lines Matching full:csky
1 //===-- CSKYInstrInfo.h - CSKY Instruction Information --------*- C++ -*---===//
9 // This file contains the CSKY implementation of the TargetInstrInfo class.
20 #define DEBUG_TYPE "csky-instr-info"
28 : CSKYGenInstrInfo(CSKY::ADJCALLSTACKDOWN, CSKY::ADJCALLSTACKUP), STI(STI) { in CSKYInstrInfo()
163 "CSKY branch conditions have two components!"); in insertBranch()
167 MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB); in insertBranch()
184 MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB); in insertBranch()
194 case CSKY::BT32: in getOppositeBranchOpc()
195 return CSKY::BF32; in getOppositeBranchOpc()
196 case CSKY::BT16: in getOppositeBranchOpc()
197 return CSKY::BF16; in getOppositeBranchOpc()
198 case CSKY::BF32: in getOppositeBranchOpc()
199 return CSKY::BT32; in getOppositeBranchOpc()
200 case CSKY::BF16: in getOppositeBranchOpc()
201 return CSKY::BT16; in getOppositeBranchOpc()
202 case CSKY::BHZ32: in getOppositeBranchOpc()
203 return CSKY::BLSZ32; in getOppositeBranchOpc()
204 case CSKY::BHSZ32: in getOppositeBranchOpc()
205 return CSKY::BLZ32; in getOppositeBranchOpc()
206 case CSKY::BLZ32: in getOppositeBranchOpc()
207 return CSKY::BHSZ32; in getOppositeBranchOpc()
208 case CSKY::BLSZ32: in getOppositeBranchOpc()
209 return CSKY::BHZ32; in getOppositeBranchOpc()
210 case CSKY::BNEZ32: in getOppositeBranchOpc()
211 return CSKY::BEZ32; in getOppositeBranchOpc()
212 case CSKY::BEZ32: in getOppositeBranchOpc()
213 return CSKY::BNEZ32; in getOppositeBranchOpc()
235 DstReg = MRI.createVirtualRegister(&CSKY::GPRRegClass); in movImm()
238 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI32), DstReg) in movImm()
242 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
246 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
249 BuildMI(MBB, MBBI, DL, get(CSKY::ORI32), DstReg) in movImm()
256 DstReg = MRI.createVirtualRegister(&CSKY::mGPRRegClass); in movImm()
258 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
262 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
265 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
270 BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg) in movImm()
275 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
278 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
283 BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg) in movImm()
287 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
292 BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg) in movImm()
297 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
300 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
305 BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg) in movImm()
309 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
314 BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg) in movImm()
318 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
323 BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg) in movImm()
338 case CSKY::LD16B: in isLoadFromStackSlot()
339 case CSKY::LD16H: in isLoadFromStackSlot()
340 case CSKY::LD16W: in isLoadFromStackSlot()
341 case CSKY::LD32B: in isLoadFromStackSlot()
342 case CSKY::LD32BS: in isLoadFromStackSlot()
343 case CSKY::LD32H: in isLoadFromStackSlot()
344 case CSKY::LD32HS: in isLoadFromStackSlot()
345 case CSKY::LD32W: in isLoadFromStackSlot()
346 case CSKY::FLD_S: in isLoadFromStackSlot()
347 case CSKY::FLD_D: in isLoadFromStackSlot()
348 case CSKY::f2FLD_S: in isLoadFromStackSlot()
349 case CSKY::f2FLD_D: in isLoadFromStackSlot()
350 case CSKY::RESTORE_CARRY: in isLoadFromStackSlot()
368 case CSKY::ST16B: in isStoreToStackSlot()
369 case CSKY::ST16H: in isStoreToStackSlot()
370 case CSKY::ST16W: in isStoreToStackSlot()
371 case CSKY::ST32B: in isStoreToStackSlot()
372 case CSKY::ST32H: in isStoreToStackSlot()
373 case CSKY::ST32W: in isStoreToStackSlot()
374 case CSKY::FST_S: in isStoreToStackSlot()
375 case CSKY::FST_D: in isStoreToStackSlot()
376 case CSKY::f2FST_S: in isStoreToStackSlot()
377 case CSKY::f2FST_D: in isStoreToStackSlot()
378 case CSKY::SPILL_CARRY: in isStoreToStackSlot()
407 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
408 Opcode = CSKY::ST32W; // Optimize for 16bit in storeRegToStackSlot()
409 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
410 Opcode = CSKY::SPILL_CARRY; in storeRegToStackSlot()
412 } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
413 Opcode = CSKY::FST_S; in storeRegToStackSlot()
414 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
415 Opcode = CSKY::FST_D; in storeRegToStackSlot()
416 else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
417 Opcode = CSKY::f2FST_S; in storeRegToStackSlot()
418 else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
419 Opcode = CSKY::f2FST_D; in storeRegToStackSlot()
451 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
452 Opcode = CSKY::LD32W; in loadRegFromStackSlot()
453 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
454 Opcode = CSKY::RESTORE_CARRY; in loadRegFromStackSlot()
456 } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
457 Opcode = CSKY::FLD_S; in loadRegFromStackSlot()
458 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
459 Opcode = CSKY::FLD_D; in loadRegFromStackSlot()
460 else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
461 Opcode = CSKY::f2FLD_S; in loadRegFromStackSlot()
462 else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
463 Opcode = CSKY::f2FLD_D; in loadRegFromStackSlot()
482 if (CSKY::GPRRegClass.contains(SrcReg) && in copyPhysReg()
483 CSKY::CARRYRegClass.contains(DestReg)) { in copyPhysReg()
485 BuildMI(MBB, I, DL, get(CSKY::BTSTI32), DestReg) in copyPhysReg()
489 assert(SrcReg < CSKY::R8); in copyPhysReg()
490 BuildMI(MBB, I, DL, get(CSKY::BTSTI16), DestReg) in copyPhysReg()
497 if (CSKY::CARRYRegClass.contains(SrcReg) && in copyPhysReg()
498 CSKY::GPRRegClass.contains(DestReg)) { in copyPhysReg()
501 BuildMI(MBB, I, DL, get(CSKY::MVC32), DestReg) in copyPhysReg()
504 assert(DestReg < CSKY::R16); in copyPhysReg()
505 assert(DestReg < CSKY::R8); in copyPhysReg()
506 BuildMI(MBB, I, DL, get(CSKY::MOVI16), DestReg).addImm(0); in copyPhysReg()
507 BuildMI(MBB, I, DL, get(CSKY::ADDC16)) in copyPhysReg()
513 BuildMI(MBB, I, DL, get(CSKY::BTSTI16)) in copyPhysReg()
522 if (CSKY::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
523 Opcode = STI.hasE2() ? CSKY::MOV32 : CSKY::MOV16; in copyPhysReg()
524 else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
525 Opcode = CSKY::FMOV_S; in copyPhysReg()
526 else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
527 Opcode = CSKY::f2FMOV_S; in copyPhysReg()
528 else if (v2df && CSKY::sFPR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
529 Opcode = CSKY::FMOV_D; in copyPhysReg()
530 else if (v3df && CSKY::FPR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
531 Opcode = CSKY::f2FMOV_D; in copyPhysReg()
532 else if (v2sf && CSKY::sFPR32RegClass.contains(SrcReg) && in copyPhysReg()
533 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
534 Opcode = CSKY::FMFVRL; in copyPhysReg()
535 else if (v3sf && CSKY::FPR32RegClass.contains(SrcReg) && in copyPhysReg()
536 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
537 Opcode = CSKY::f2FMFVRL; in copyPhysReg()
538 else if (v2df && CSKY::sFPR64RegClass.contains(SrcReg) && in copyPhysReg()
539 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
540 Opcode = CSKY::FMFVRL_D; in copyPhysReg()
541 else if (v3df && CSKY::FPR64RegClass.contains(SrcReg) && in copyPhysReg()
542 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
543 Opcode = CSKY::f2FMFVRL_D; in copyPhysReg()
544 else if (v2sf && CSKY::GPRRegClass.contains(SrcReg) && in copyPhysReg()
545 CSKY::sFPR32RegClass.contains(DestReg)) in copyPhysReg()
546 Opcode = CSKY::FMTVRL; in copyPhysReg()
547 else if (v3sf && CSKY::GPRRegClass.contains(SrcReg) && in copyPhysReg()
548 CSKY::FPR32RegClass.contains(DestReg)) in copyPhysReg()
549 Opcode = CSKY::f2FMTVRL; in copyPhysReg()
550 else if (v2df && CSKY::GPRRegClass.contains(SrcReg) && in copyPhysReg()
551 CSKY::sFPR64RegClass.contains(DestReg)) in copyPhysReg()
552 Opcode = CSKY::FMTVRL_D; in copyPhysReg()
553 else if (v3df && CSKY::GPRRegClass.contains(SrcReg) && in copyPhysReg()
554 CSKY::FPR64RegClass.contains(DestReg)) in copyPhysReg()
555 Opcode = CSKY::f2FMTVRL_D; in copyPhysReg()
590 BuildMI(FirstMBB, MBBI, DL, get(CSKY::LRW32), CSKY::R28) in getGlobalBaseReg()
594 GlobalBaseReg = MRI.createVirtualRegister(&CSKY::GPRRegClass); in getGlobalBaseReg()
596 .addReg(CSKY::R28); in getGlobalBaseReg()
606 case CSKY::CONSTPOOL_ENTRY: in getInstSizeInBytes()
608 case CSKY::SPILL_CARRY: in getInstSizeInBytes()
609 case CSKY::RESTORE_CARRY: in getInstSizeInBytes()
610 case CSKY::PseudoTLSLA32: in getInstSizeInBytes()