Lines Matching full:csky
1 //===-- CSKYISelLowering.cpp - CSKY DAG Lowering Implementation ----------===//
9 // This file defines the interfaces that CSKY uses to lower LLVM code into a
28 #define DEBUG_TYPE "csky-isel-lowering"
34 static const MCPhysReg GPRArgRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3};
40 addRegisterClass(MVT::i32, &CSKY::GPRRegClass); in CSKYTargetLowering()
44 addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass); in CSKYTargetLowering()
46 addRegisterClass(MVT::f32, &CSKY::FPR32RegClass); in CSKYTargetLowering()
49 addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass); in CSKYTargetLowering()
51 addRegisterClass(MVT::f64, &CSKY::FPR64RegClass); in CSKYTargetLowering()
160 setStackPointerRegisterToSaveRestore(CSKY::R14); in CSKYTargetLowering()
242 RC = &CSKY::GPRRegClass; in unpackFromRegLoc()
245 RC = Subtarget.hasFPUv2SingleFloat() ? &CSKY::sFPR32RegClass in unpackFromRegLoc()
246 : &CSKY::FPR32RegClass; in unpackFromRegLoc()
249 RC = Subtarget.hasFPUv2DoubleFloat() ? &CSKY::sFPR64RegClass in unpackFromRegLoc()
250 : &CSKY::FPR64RegClass; in unpackFromRegLoc()
307 Register LoVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass); in unpack64()
311 if (VA.getLocReg() == CSKY::R3) { in unpack64()
319 Register HiVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass); in unpack64()
373 const TargetRegisterClass *RC = &CSKY::GPRRegClass; in LowerFormalArguments()
469 assert(RegLo < CSKY::R31 && "Invalid register pair"); in LowerReturn()
588 if (RegLo == CSKY::R3) { in LowerCall()
592 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT); in LowerCall()
598 assert(RegLo < CSKY::R31 && "Invalid register pair"); in LowerCall()
621 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT); in LowerCall()
821 return std::make_pair(0U, &CSKY::GPRRegClass); in getRegForInlineAsmConstraint()
823 return std::make_pair(0U, &CSKY::mGPRRegClass); in getRegForInlineAsmConstraint()
825 return std::make_pair(0U, &CSKY::sGPRRegClass); in getRegForInlineAsmConstraint()
827 return std::make_pair(CSKY::R14, &CSKY::GPRRegClass); in getRegForInlineAsmConstraint()
829 return std::make_pair(CSKY::C, &CSKY::CARRYRegClass); in getRegForInlineAsmConstraint()
834 return std::make_pair(0U, &CSKY::sFPR32RegClass); in getRegForInlineAsmConstraint()
838 return std::make_pair(0U, &CSKY::sFPR64RegClass); in getRegForInlineAsmConstraint()
842 return std::make_pair(0U, &CSKY::sFPR32RegClass); in getRegForInlineAsmConstraint()
844 return std::make_pair(0U, &CSKY::FPR32RegClass); in getRegForInlineAsmConstraint()
846 return std::make_pair(0U, &CSKY::sFPR64RegClass); in getRegForInlineAsmConstraint()
848 return std::make_pair(0U, &CSKY::FPR64RegClass); in getRegForInlineAsmConstraint()
856 return std::make_pair(CSKY::C, &CSKY::CARRYRegClass); in getRegForInlineAsmConstraint()
863 .Case("{a0}", CSKY::R0) in getRegForInlineAsmConstraint()
864 .Case("{a1}", CSKY::R1) in getRegForInlineAsmConstraint()
865 .Case("{a2}", CSKY::R2) in getRegForInlineAsmConstraint()
866 .Case("{a3}", CSKY::R3) in getRegForInlineAsmConstraint()
867 .Case("{l0}", CSKY::R4) in getRegForInlineAsmConstraint()
868 .Case("{l1}", CSKY::R5) in getRegForInlineAsmConstraint()
869 .Case("{l2}", CSKY::R6) in getRegForInlineAsmConstraint()
870 .Case("{l3}", CSKY::R7) in getRegForInlineAsmConstraint()
871 .Case("{l4}", CSKY::R8) in getRegForInlineAsmConstraint()
872 .Case("{l5}", CSKY::R9) in getRegForInlineAsmConstraint()
873 .Case("{l6}", CSKY::R10) in getRegForInlineAsmConstraint()
874 .Case("{l7}", CSKY::R11) in getRegForInlineAsmConstraint()
875 .Case("{t0}", CSKY::R12) in getRegForInlineAsmConstraint()
876 .Case("{t1}", CSKY::R13) in getRegForInlineAsmConstraint()
877 .Case("{sp}", CSKY::R14) in getRegForInlineAsmConstraint()
878 .Case("{lr}", CSKY::R15) in getRegForInlineAsmConstraint()
879 .Case("{l8}", CSKY::R16) in getRegForInlineAsmConstraint()
880 .Case("{l9}", CSKY::R17) in getRegForInlineAsmConstraint()
881 .Case("{t2}", CSKY::R18) in getRegForInlineAsmConstraint()
882 .Case("{t3}", CSKY::R19) in getRegForInlineAsmConstraint()
883 .Case("{t4}", CSKY::R20) in getRegForInlineAsmConstraint()
884 .Case("{t5}", CSKY::R21) in getRegForInlineAsmConstraint()
885 .Case("{t6}", CSKY::R22) in getRegForInlineAsmConstraint()
886 .Cases("{t7}", "{fp}", CSKY::R23) in getRegForInlineAsmConstraint()
887 .Cases("{t8}", "{top}", CSKY::R24) in getRegForInlineAsmConstraint()
888 .Cases("{t9}", "{bsp}", CSKY::R25) in getRegForInlineAsmConstraint()
889 .Case("{r26}", CSKY::R26) in getRegForInlineAsmConstraint()
890 .Case("{r27}", CSKY::R27) in getRegForInlineAsmConstraint()
891 .Cases("{gb}", "{rgb}", "{rdb}", CSKY::R28) in getRegForInlineAsmConstraint()
892 .Cases("{tb}", "{rtb}", CSKY::R29) in getRegForInlineAsmConstraint()
893 .Case("{svbr}", CSKY::R30) in getRegForInlineAsmConstraint()
894 .Case("{tls}", CSKY::R31) in getRegForInlineAsmConstraint()
895 .Default(CSKY::NoRegister); in getRegForInlineAsmConstraint()
897 if (XRegFromAlias != CSKY::NoRegister) in getRegForInlineAsmConstraint()
898 return std::make_pair(XRegFromAlias, &CSKY::GPRRegClass); in getRegForInlineAsmConstraint()
909 .Cases("{fr0}", "{vr0}", CSKY::F0_32) in getRegForInlineAsmConstraint()
910 .Cases("{fr1}", "{vr1}", CSKY::F1_32) in getRegForInlineAsmConstraint()
911 .Cases("{fr2}", "{vr2}", CSKY::F2_32) in getRegForInlineAsmConstraint()
912 .Cases("{fr3}", "{vr3}", CSKY::F3_32) in getRegForInlineAsmConstraint()
913 .Cases("{fr4}", "{vr4}", CSKY::F4_32) in getRegForInlineAsmConstraint()
914 .Cases("{fr5}", "{vr5}", CSKY::F5_32) in getRegForInlineAsmConstraint()
915 .Cases("{fr6}", "{vr6}", CSKY::F6_32) in getRegForInlineAsmConstraint()
916 .Cases("{fr7}", "{vr7}", CSKY::F7_32) in getRegForInlineAsmConstraint()
917 .Cases("{fr8}", "{vr8}", CSKY::F8_32) in getRegForInlineAsmConstraint()
918 .Cases("{fr9}", "{vr9}", CSKY::F9_32) in getRegForInlineAsmConstraint()
919 .Cases("{fr10}", "{vr10}", CSKY::F10_32) in getRegForInlineAsmConstraint()
920 .Cases("{fr11}", "{vr11}", CSKY::F11_32) in getRegForInlineAsmConstraint()
921 .Cases("{fr12}", "{vr12}", CSKY::F12_32) in getRegForInlineAsmConstraint()
922 .Cases("{fr13}", "{vr13}", CSKY::F13_32) in getRegForInlineAsmConstraint()
923 .Cases("{fr14}", "{vr14}", CSKY::F14_32) in getRegForInlineAsmConstraint()
924 .Cases("{fr15}", "{vr15}", CSKY::F15_32) in getRegForInlineAsmConstraint()
925 .Cases("{fr16}", "{vr16}", CSKY::F16_32) in getRegForInlineAsmConstraint()
926 .Cases("{fr17}", "{vr17}", CSKY::F17_32) in getRegForInlineAsmConstraint()
927 .Cases("{fr18}", "{vr18}", CSKY::F18_32) in getRegForInlineAsmConstraint()
928 .Cases("{fr19}", "{vr19}", CSKY::F19_32) in getRegForInlineAsmConstraint()
929 .Cases("{fr20}", "{vr20}", CSKY::F20_32) in getRegForInlineAsmConstraint()
930 .Cases("{fr21}", "{vr21}", CSKY::F21_32) in getRegForInlineAsmConstraint()
931 .Cases("{fr22}", "{vr22}", CSKY::F22_32) in getRegForInlineAsmConstraint()
932 .Cases("{fr23}", "{vr23}", CSKY::F23_32) in getRegForInlineAsmConstraint()
933 .Cases("{fr24}", "{vr24}", CSKY::F24_32) in getRegForInlineAsmConstraint()
934 .Cases("{fr25}", "{vr25}", CSKY::F25_32) in getRegForInlineAsmConstraint()
935 .Cases("{fr26}", "{vr26}", CSKY::F26_32) in getRegForInlineAsmConstraint()
936 .Cases("{fr27}", "{vr27}", CSKY::F27_32) in getRegForInlineAsmConstraint()
937 .Cases("{fr28}", "{vr28}", CSKY::F28_32) in getRegForInlineAsmConstraint()
938 .Cases("{fr29}", "{vr29}", CSKY::F29_32) in getRegForInlineAsmConstraint()
939 .Cases("{fr30}", "{vr30}", CSKY::F30_32) in getRegForInlineAsmConstraint()
940 .Cases("{fr31}", "{vr31}", CSKY::F31_32) in getRegForInlineAsmConstraint()
941 .Default(CSKY::NoRegister); in getRegForInlineAsmConstraint()
942 if (FReg != CSKY::NoRegister) { in getRegForInlineAsmConstraint()
943 assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 && "Unknown fp-reg"); in getRegForInlineAsmConstraint()
944 unsigned RegNo = FReg - CSKY::F0_32; in getRegForInlineAsmConstraint()
945 unsigned DReg = CSKY::F0_64 + RegNo; in getRegForInlineAsmConstraint()
948 return std::make_pair(DReg, &CSKY::sFPR64RegClass); in getRegForInlineAsmConstraint()
950 return std::make_pair(DReg, &CSKY::FPR64RegClass); in getRegForInlineAsmConstraint()
952 return std::make_pair(FReg, &CSKY::sFPR32RegClass); in getRegForInlineAsmConstraint()
954 return std::make_pair(FReg, &CSKY::FPR32RegClass); in getRegForInlineAsmConstraint()
1013 BuildMI(*BB, BB->begin(), DL, TII.get(CSKY::PHI), MI.getOperand(0).getReg()) in emitSelectPseudo()
1030 case CSKY::FSELS: in EmitInstrWithCustomInserter()
1031 case CSKY::FSELD: in EmitInstrWithCustomInserter()
1033 return emitSelectPseudo(MI, BB, CSKY::BT32); in EmitInstrWithCustomInserter()
1035 return emitSelectPseudo(MI, BB, CSKY::BT16); in EmitInstrWithCustomInserter()
1036 case CSKY::ISEL32: in EmitInstrWithCustomInserter()
1037 return emitSelectPseudo(MI, BB, CSKY::BT32); in EmitInstrWithCustomInserter()
1038 case CSKY::ISEL16: in EmitInstrWithCustomInserter()
1039 return emitSelectPseudo(MI, BB, CSKY::BT16); in EmitInstrWithCustomInserter()
1257 return CSKY::R0; in getExceptionPointerRegister()
1262 return CSKY::R1; in getExceptionSelectorRegister()
1321 auto *LRWGRS = DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty}, in getStaticTLSAddr()
1328 Load = SDValue(DAG.getMachineNode(CSKY::LRW32, DL, Ty, CAddr), 0); in getStaticTLSAddr()
1332 SDValue TPReg = DAG.getRegister(CSKY::R31, MVT::i32); in getStaticTLSAddr()
1354 DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty}, {Addr, PICLabel}); in getDynamicTLSAddr()