Lines Matching full:csky
1 //===-- CSKYFrameLowering.cpp - CSKY Frame Information ------------------===//
9 // This file contains the CSKY implementation of TargetFrameLowering class.
27 #define DEBUG_TYPE "csky-frame-lowering"
30 static Register getFPReg(const CSKYSubtarget &STI) { return CSKY::R8; } in getFPReg()
34 static Register getBPReg(const CSKYSubtarget &STI) { return CSKY::R7; } in getBPReg()
89 Register SPReg = CSKY::R14; in emitPrologue()
97 BuildMI(MBB, MBBI, DL, TII->get(CSKY::NIE)); in emitPrologue()
173 BuildMI(MBB, MBBI, DL, TII->get(CSKY::ANDNI32), SPReg) in emitPrologue()
181 MF.getRegInfo().createVirtualRegister(&CSKY::GPRRegClass); in emitPrologue()
182 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSRI32), VR) in emitPrologue()
185 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSLI32), SPReg) in emitPrologue()
190 MF.getRegInfo().createVirtualRegister(&CSKY::mGPRRegClass); in emitPrologue()
191 BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), VR).addReg(SPReg); in emitPrologue()
192 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSRI16), VR) in emitPrologue()
195 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSLI16), VR) in emitPrologue()
198 BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), SPReg).addReg(VR); in emitPrologue()
229 Register SPReg = CSKY::R14; in emitEpilogue()
298 if (MI.getOpcode() == CSKY::SPILL_CARRY || in estimateRSStackSizeLimit()
299 MI.getOpcode() == CSKY::RESTORE_CARRY || in estimateRSStackSizeLimit()
300 MI.getOpcode() == CSKY::STORE_PAIR || in estimateRSStackSizeLimit()
301 MI.getOpcode() == CSKY::LOAD_PAIR) { in estimateRSStackSizeLimit()
306 if (MI.getOpcode() == CSKY::ADDI32) { in estimateRSStackSizeLimit()
311 if (MI.getOpcode() == CSKY::ADDI16XZ) { in estimateRSStackSizeLimit()
318 if (MI.getOpcode() == CSKY::ADDI16) in estimateRSStackSizeLimit()
369 SavedRegs.set(CSKY::R8); in determineCalleeSaves()
373 SavedRegs.set(CSKY::R7); in determineCalleeSaves()
380 static const MCPhysReg CSRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3, in determineCalleeSaves()
381 CSKY::R12, CSKY::R13, 0}; in determineCalleeSaves()
388 static const MCPhysReg CSHRegs[] = {CSKY::R18, CSKY::R19, CSKY::R20, in determineCalleeSaves()
389 CSKY::R21, CSKY::R22, CSKY::R23, in determineCalleeSaves()
390 CSKY::R24, CSKY::R25, 0}; in determineCalleeSaves()
397 CSKY::F8_32, CSKY::F9_32, CSKY::F10_32, in determineCalleeSaves()
398 CSKY::F11_32, CSKY::F12_32, CSKY::F13_32, in determineCalleeSaves()
399 CSKY::F14_32, CSKY::F15_32, 0}; in determineCalleeSaves()
401 CSKY::F8_64, CSKY::F9_64, CSKY::F10_64, in determineCalleeSaves()
402 CSKY::F11_64, CSKY::F12_64, CSKY::F13_64, in determineCalleeSaves()
403 CSKY::F14_64, CSKY::F15_64, 0}; in determineCalleeSaves()
415 if (CSKY::FPR32RegClass.contains(Regs[i]) || in determineCalleeSaves()
416 CSKY::FPR64RegClass.contains(Regs[i])) { in determineCalleeSaves()
440 const TargetRegisterClass *RC = &CSKY::GPRRegClass; in determineCalleeSaves()
451 SavedRegs.set(CSKY::R15); in determineCalleeSaves()
453 CFI->setLRIsSpilled(SavedRegs.test(CSKY::R15)); in determineCalleeSaves()
513 Register SPReg = CSKY::R14; in eliminateCallFramePseudoInstr()
528 if (MI->getOpcode() == CSKY::ADJCALLSTACKDOWN) in eliminateCallFramePseudoInstr()
550 BuildMI(MBB, MBBI, DL, TII->get(Val < 0 ? CSKY::SUBI32 : CSKY::ADDI32), in adjustReg()
557 TII->get(Val < 0 ? CSKY::SUBI16SPSP : CSKY::ADDI16SPSP), CSKY::R14) in adjustReg()
558 .addReg(CSKY::R14, RegState::Kill) in adjustReg()
566 Op = Val < 0 ? CSKY::SUBU32 : CSKY::ADDU32; in adjustReg()
569 Op = Val < 0 ? CSKY::SUBU16XZ : CSKY::ADDU16XZ; in adjustReg()
600 FrameReg = CSKY::R14; in getFrameIndexReference()
605 FrameReg = hasBP(MF) ? getBPReg(STI) : CSKY::R14; in getFrameIndexReference()
616 FrameReg = hasBP(MF) ? getBPReg(STI) : CSKY::R14; in getFrameIndexReference()