Lines Matching refs:Enable
23 "Enable FPUv2 single float instructions">;
26 "Enable FPUv2 single float instructions">;
30 "Enable FPUv2 double float instructions">;
33 "Enable FPUv2 double float instructions">;
36 "Enable float divide instructions">;
39 "Enable float divide instructions">;
43 "Enable FPUv3 half word converting instructions">;
46 "Enable FPUv3 half word converting instructions">;
50 "Enable FPUv3 half precision operate instructions">;
53 "Enable FPUv3 half precision operate instructions">;
57 "Enable FPUv3 single float instructions">;
60 "Enable FPUv3 single float instructions">;
64 "Enable FPUv3 double float instructions">;
67 "Enable FPUv3 double float instructions">;
100 "Enable divide instrutions">;
103 "Enable divide instrutions">;
106 "Enable multiple load/store instrutions">;
109 "Enable multiple load/store instrutions">;
112 "Enable push/pop instrutions">;
115 "Enable push/pop instrutions">;
118 : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instrutions">;
121 "Enable DSP instrutions">;
136 "Enable DSP V2.0 instrutions">;
139 "Enable DSP V2.0 instrutions">;
142 "Enable DSP Silan instrutions">;
145 "Enable DSP Silan instrutions">;
162 "Enable trust instructions">;
165 "Enable trust instructions">;
168 : SubtargetFeature<"java", "HasJAVA", "true", "Enable java instructions">;
171 "Enable java instructions">;
174 : SubtargetFeature<"cache", "HasCache", "true", "Enable cache">;
177 "Enable cache">;
180 : SubtargetFeature<"nvic", "HasNVIC", "true", "Enable NVIC">;
183 "Enable NVIC">;
186 "Enable doloop instructions">;
189 "Enable doloop instructions">;
193 "true", "Enable r16-r31 registers">;
196 "Enable r16-r31 registers">;
205 "Enable vdsp-v2 instructions">;
208 "Enable vdsp-v2 instructions">;
226 "Enable TLS Pointer register">;
229 "Enable TLS Pointer register">;
235 "true", "Enable interrput attribute">;
239 "Enable interrput attribute">;
260 "Enable 128bit vdsp-v1 instructions">;
263 "Enable 128bit vdsp-v1 instructions">;