Lines Matching refs:DstIsDead
156 bool DstIsDead = MI.getOperand(0).isDead(); in expandArith() local
164 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
170 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
189 bool DstIsDead = MI.getOperand(0).isDead(); in expandLogic() local
198 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
207 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
248 bool DstIsDead = MI.getOperand(0).isDead(); in expandLogicImm() local
259 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogicImm()
273 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogicImm()
308 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
315 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
320 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
362 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
374 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
383 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
427 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
436 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
444 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
460 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
468 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
475 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
481 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
566 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
573 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
577 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
617 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
624 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
628 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
708 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
718 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
724 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
741 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
751 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
757 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1205 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
1221 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1240 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
1256 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1384 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
1395 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1400 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1495 bool DstIsDead = MI.getOperand(0).isDead(); in expandROLBRd() local
1505 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandROLBRd()
1511 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandROLBRd()
1565 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
1574 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1580 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1599 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
1607 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1622 bool DstIsDead = MI.getOperand(0).isDead(); in expandLSLW4Rd() local
1630 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1633 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1639 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1648 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1657 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1666 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1680 bool DstIsDead = MI.getOperand(0).isDead(); in expandLSLW8Rd() local
1687 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW8Rd()
1693 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW8Rd()
1707 bool DstIsDead = MI.getOperand(0).isDead(); in expandLSLW12Rd() local
1714 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1719 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1725 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1734 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1766 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
1775 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1780 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1798 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
1806 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1820 bool DstIsDead = MI.getOperand(0).isDead(); in expandLSRW4Rd() local
1828 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1831 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1837 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1846 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1855 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1864 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1878 bool DstIsDead = MI.getOperand(0).isDead(); in expandLSRW8Rd() local
1885 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW8Rd()
1891 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW8Rd()
1905 bool DstIsDead = MI.getOperand(0).isDead(); in expandLSRW12Rd() local
1912 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1917 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1923 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1932 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1976 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
1985 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1990 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2008 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
2016 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2030 bool DstIsDead = MI.getOperand(0).isDead(); in expandASRW7Rd() local
2042 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
2048 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
2053 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
2060 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
2077 bool DstIsDead = MI.getOperand(0).isDead(); in expandASRW8Rd() local
2084 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
2089 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
2096 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
2112 bool DstIsDead = MI.getOperand(0).isDead(); in expandASRW14Rd() local
2125 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2131 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2137 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2143 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2149 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2166 bool DstIsDead = MI.getOperand(0).isDead(); in expandASRW15Rd() local
2183 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW15Rd()
2193 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW15Rd()
2222 bool DstIsDead = MI.getOperand(0).isDead(); in expandLSLB7Rd() local
2231 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2237 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2243 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2272 bool DstIsDead = MI.getOperand(0).isDead(); in expandLSRB7Rd() local
2281 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2288 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2294 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2324 bool DstIsDead = MI.getOperand(0).isDead(); in expandASRB6Rd() local
2339 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2344 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2349 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2362 bool DstIsDead = MI.getOperand(0).isDead(); in expandASRB7Rd() local
2370 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB7Rd()
2376 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB7Rd()
2423 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
2430 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2448 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2475 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
2482 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2488 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2504 bool DstIsDead = MI.getOperand(0).isDead(); in expand() local
2512 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2518 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()