Lines Matching full:arm
54 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0); in getNop()
93 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
141 get(ARM::t2CSEL), DestReg) in optimizeSelect()
156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
159 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
179 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
180 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
189 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
195 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
199 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
200 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
223 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
224 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
232 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
238 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass); in loadRegFromStackSlot()
241 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); in loadRegFromStackSlot()
242 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
243 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
261 expandLoadStackGuardBase(MI, ARM::t2MRC, ARM::t2LDRi12); in expandLoadStackGuard()
267 expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12); in expandLoadStackGuard()
269 expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12); in expandLoadStackGuard()
271 expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12); in expandLoadStackGuard()
279 case ARM::MVE_VMAXNMAf16: in commuteInstructionImpl()
280 case ARM::MVE_VMAXNMAf32: in commuteInstructionImpl()
281 case ARM::MVE_VMINNMAf16: in commuteInstructionImpl()
282 case ARM::MVE_VMINNMAf32: in commuteInstructionImpl()
298 case ARM::t2BTI: in isSchedulingBoundary()
299 case ARM::t2PAC: in isSchedulingBoundary()
300 case ARM::t2PACBTI: in isSchedulingBoundary()
301 case ARM::t2SG: in isSchedulingBoundary()
317 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitT2RegPlusImmediate()
328 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
334 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
340 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) in emitT2RegPlusImmediate()
349 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) in emitT2RegPlusImmediate()
361 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) in emitT2RegPlusImmediate()
375 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
377 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitT2RegPlusImmediate()
381 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
385 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate()
389 if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) { in emitT2RegPlusImmediate()
391 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
401 bool ToSP = DestReg == ARM::SP; in emitT2RegPlusImmediate()
402 unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri; in emitT2RegPlusImmediate()
403 unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri; in emitT2RegPlusImmediate()
404 unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12; in emitT2RegPlusImmediate()
405 unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12; in emitT2RegPlusImmediate()
443 case ARM::t2LDRi12: return ARM::t2LDRi8; in negativeOffsetOpcode()
444 case ARM::t2LDRHi12: return ARM::t2LDRHi8; in negativeOffsetOpcode()
445 case ARM::t2LDRBi12: return ARM::t2LDRBi8; in negativeOffsetOpcode()
446 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8; in negativeOffsetOpcode()
447 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8; in negativeOffsetOpcode()
448 case ARM::t2STRi12: return ARM::t2STRi8; in negativeOffsetOpcode()
449 case ARM::t2STRBi12: return ARM::t2STRBi8; in negativeOffsetOpcode()
450 case ARM::t2STRHi12: return ARM::t2STRHi8; in negativeOffsetOpcode()
451 case ARM::t2PLDi12: return ARM::t2PLDi8; in negativeOffsetOpcode()
452 case ARM::t2PLDWi12: return ARM::t2PLDWi8; in negativeOffsetOpcode()
453 case ARM::t2PLIi12: return ARM::t2PLIi8; in negativeOffsetOpcode()
455 case ARM::t2LDRi8: in negativeOffsetOpcode()
456 case ARM::t2LDRHi8: in negativeOffsetOpcode()
457 case ARM::t2LDRBi8: in negativeOffsetOpcode()
458 case ARM::t2LDRSHi8: in negativeOffsetOpcode()
459 case ARM::t2LDRSBi8: in negativeOffsetOpcode()
460 case ARM::t2STRi8: in negativeOffsetOpcode()
461 case ARM::t2STRBi8: in negativeOffsetOpcode()
462 case ARM::t2STRHi8: in negativeOffsetOpcode()
463 case ARM::t2PLDi8: in negativeOffsetOpcode()
464 case ARM::t2PLDWi8: in negativeOffsetOpcode()
465 case ARM::t2PLIi8: in negativeOffsetOpcode()
477 case ARM::t2LDRi8: return ARM::t2LDRi12; in positiveOffsetOpcode()
478 case ARM::t2LDRHi8: return ARM::t2LDRHi12; in positiveOffsetOpcode()
479 case ARM::t2LDRBi8: return ARM::t2LDRBi12; in positiveOffsetOpcode()
480 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12; in positiveOffsetOpcode()
481 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12; in positiveOffsetOpcode()
482 case ARM::t2STRi8: return ARM::t2STRi12; in positiveOffsetOpcode()
483 case ARM::t2STRBi8: return ARM::t2STRBi12; in positiveOffsetOpcode()
484 case ARM::t2STRHi8: return ARM::t2STRHi12; in positiveOffsetOpcode()
485 case ARM::t2PLDi8: return ARM::t2PLDi12; in positiveOffsetOpcode()
486 case ARM::t2PLDWi8: return ARM::t2PLDWi12; in positiveOffsetOpcode()
487 case ARM::t2PLIi8: return ARM::t2PLIi12; in positiveOffsetOpcode()
489 case ARM::t2LDRi12: in positiveOffsetOpcode()
490 case ARM::t2LDRHi12: in positiveOffsetOpcode()
491 case ARM::t2LDRBi12: in positiveOffsetOpcode()
492 case ARM::t2LDRSHi12: in positiveOffsetOpcode()
493 case ARM::t2LDRSBi12: in positiveOffsetOpcode()
494 case ARM::t2STRi12: in positiveOffsetOpcode()
495 case ARM::t2STRBi12: in positiveOffsetOpcode()
496 case ARM::t2STRHi12: in positiveOffsetOpcode()
497 case ARM::t2PLDi12: in positiveOffsetOpcode()
498 case ARM::t2PLDWi12: in positiveOffsetOpcode()
499 case ARM::t2PLIi12: in positiveOffsetOpcode()
511 case ARM::t2LDRs: return ARM::t2LDRi12; in immediateOffsetOpcode()
512 case ARM::t2LDRHs: return ARM::t2LDRHi12; in immediateOffsetOpcode()
513 case ARM::t2LDRBs: return ARM::t2LDRBi12; in immediateOffsetOpcode()
514 case ARM::t2LDRSHs: return ARM::t2LDRSHi12; in immediateOffsetOpcode()
515 case ARM::t2LDRSBs: return ARM::t2LDRSBi12; in immediateOffsetOpcode()
516 case ARM::t2STRs: return ARM::t2STRi12; in immediateOffsetOpcode()
517 case ARM::t2STRBs: return ARM::t2STRBi12; in immediateOffsetOpcode()
518 case ARM::t2STRHs: return ARM::t2STRHi12; in immediateOffsetOpcode()
519 case ARM::t2PLDs: return ARM::t2PLDi12; in immediateOffsetOpcode()
520 case ARM::t2PLDWs: return ARM::t2PLDWi12; in immediateOffsetOpcode()
521 case ARM::t2PLIs: return ARM::t2PLIi12; in immediateOffsetOpcode()
523 case ARM::t2LDRi12: in immediateOffsetOpcode()
524 case ARM::t2LDRHi12: in immediateOffsetOpcode()
525 case ARM::t2LDRBi12: in immediateOffsetOpcode()
526 case ARM::t2LDRSHi12: in immediateOffsetOpcode()
527 case ARM::t2LDRSBi12: in immediateOffsetOpcode()
528 case ARM::t2STRi12: in immediateOffsetOpcode()
529 case ARM::t2STRBi12: in immediateOffsetOpcode()
530 case ARM::t2STRHi12: in immediateOffsetOpcode()
531 case ARM::t2PLDi12: in immediateOffsetOpcode()
532 case ARM::t2PLDWi12: in immediateOffsetOpcode()
533 case ARM::t2PLIi12: in immediateOffsetOpcode()
534 case ARM::t2LDRi8: in immediateOffsetOpcode()
535 case ARM::t2LDRHi8: in immediateOffsetOpcode()
536 case ARM::t2LDRBi8: in immediateOffsetOpcode()
537 case ARM::t2LDRSHi8: in immediateOffsetOpcode()
538 case ARM::t2LDRSBi8: in immediateOffsetOpcode()
539 case ARM::t2STRi8: in immediateOffsetOpcode()
540 case ARM::t2STRBi8: in immediateOffsetOpcode()
541 case ARM::t2STRHi8: in immediateOffsetOpcode()
542 case ARM::t2PLDi8: in immediateOffsetOpcode()
543 case ARM::t2PLDWi8: in immediateOffsetOpcode()
544 case ARM::t2PLIi8: in immediateOffsetOpcode()
566 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR) in rewriteT2FrameIndex()
569 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm; in rewriteT2FrameIndex()
570 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { in rewriteT2FrameIndex()
575 !MI.definesRegister(ARM::CPSR, /*TRI=*/nullptr)) { in rewriteT2FrameIndex()
577 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
587 bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12); in rewriteT2FrameIndex()
592 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
594 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
610 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex()
611 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12; in rewriteT2FrameIndex()
789 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) in getITInstrPredicate()
798 if (ARM::isVpred(MCID.operands()[i].OperandType)) in findFirstVPTPredOperandIdx()
837 ARM::PredBlockMask BlockMask = ARM::PredBlockMask::T; in recomputeVPTBlockMask()