58 static inline bool isVCTP(const MachineInstr *MI) {  in isVCTP()  argument
59   switch (MI->getOpcode()) {  in isVCTP()
71 static inline bool isDoLoopStart(const MachineInstr &MI) {  in isDoLoopStart()  argument
72   return MI.getOpcode() == ARM::t2DoLoopStart ||  in isDoLoopStart()
73          MI.getOpcode() == ARM::t2DoLoopStartTP;  in isDoLoopStart()
76 static inline bool isWhileLoopStart(const MachineInstr &MI) {  in isWhileLoopStart()  argument
77   return MI.getOpcode() == ARM::t2WhileLoopStart ||  in isWhileLoopStart()
78          MI.getOpcode() == ARM::t2WhileLoopStartLR ||  in isWhileLoopStart()
79          MI.getOpcode() == ARM::t2WhileLoopStartTP;  in isWhileLoopStart()
82 static inline bool isLoopStart(const MachineInstr &MI) {  in isLoopStart()  argument
83   return isDoLoopStart(MI) || isWhileLoopStart(MI);  in isLoopStart()
87 inline MachineBasicBlock *getWhileLoopStartTargetBB(const MachineInstr &MI) {  in getWhileLoopStartTargetBB()  argument
88   assert(isWhileLoopStart(MI) && "Expected WhileLoopStart!");  in getWhileLoopStartTargetBB()
89   unsigned Op = MI.getOpcode() == ARM::t2WhileLoopStartTP ? 3 : 2;  in getWhileLoopStartTargetBB()
90   return MI.getOperand(Op).getMBB();  in getWhileLoopStartTargetBB()
98 inline void RevertWhileLoopStartLR(MachineInstr *MI, const TargetInstrInfo *TII,
101   MachineBasicBlock *MBB = MI->getParent();
102   assert((MI->getOpcode() == ARM::t2WhileLoopStartLR ||
103           MI->getOpcode() == ARM::t2WhileLoopStartTP) &&
109         BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri));
110     MIB.add(MI->getOperand(1));
116         BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
117     MIB.add(MI->getOperand(0));
118     MIB.add(MI->getOperand(1));
127       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
128   MIB.addMBB(getWhileLoopStartTargetBB(*MI)); // branch target
132   MI->eraseFromParent();
135 inline void RevertDoLoopStart(MachineInstr *MI, const TargetInstrInfo *TII) {  in RevertDoLoopStart()  argument
136   MachineBasicBlock *MBB = MI->getParent();  in RevertDoLoopStart()
137   BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::tMOVr))  in RevertDoLoopStart()
138       .add(MI->getOperand(0))  in RevertDoLoopStart()
139       .add(MI->getOperand(1))  in RevertDoLoopStart()
142   MI->eraseFromParent();  in RevertDoLoopStart()
145 inline void RevertLoopDec(MachineInstr *MI, const TargetInstrInfo *TII,
147   MachineBasicBlock *MBB = MI->getParent();
150       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
151   MIB.add(MI->getOperand(0));
152   MIB.add(MI->getOperand(1));
153   MIB.add(MI->getOperand(2));
163   MI->eraseFromParent();
167 inline void RevertLoopEnd(MachineInstr *MI, const TargetInstrInfo *TII,
169   MachineBasicBlock *MBB = MI->getParent();
174         BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri));
175     MIB.add(MI->getOperand(0));
183       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
184   MIB.add(MI->getOperand(1)); // branch target
187   MI->eraseFromParent();