Lines Matching +full:0 +full:xf0ffffff
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
71 // is in the MCOperand format in which 1 means 'else' and 0 'then'.
75 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); in setITState()
117 bool T = ((Mask >> Pos) & 1) == 0; in setVPTState()
722 // HVC is undefined if condition = 0xf otherwise upredictable in checkDecodedInstruction()
723 // if condition != 0xe in checkDecodedInstruction()
724 uint32_t Cond = (Insn >> 28) & 0xF; in checkDecodedInstruction()
725 if (Cond == 0xF) in checkDecodedInstruction()
727 if (Cond != 0xE) in checkDecodedInstruction()
739 if (MI.getOperand(0).getReg() == ARM::SP && in checkDecodedInstruction()
756 // instruction if and only if its value is less than 0xE800. in suggestBytesToSkip()
772 return Insn16 < 0xE800 ? 2 : 4; in suggestBytesToSkip()
796 Size = 0; in getARMInstruction()
830 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) in getARMInstruction()
865 isBranch, /*Offset=*/0, /*OpSize=*/0, in tryAddingSymbolicOperand()
891 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) { in AddThumb1SBit()
895 if (i > 0 && MCID.operands()[i - 1].isPredicate()) in AddThumb1SBit()
897 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
902 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
907 for (unsigned i = 0; i < MCID.NumOperands; ++i) { in isVectorPredicable()
949 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
986 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) { in AddThumbPredicate()
995 MI.insert(CCI, MCOperand::createReg(0)); in AddThumbPredicate()
1004 for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) { in AddThumbPredicate()
1013 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); in AddThumbPredicate()
1017 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); in AddThumbPredicate()
1021 assert(TiedOp >= 0 && in AddThumbPredicate()
1042 if (CC == 0xF) in UpdateThumbVFPPredicate()
1055 for (unsigned i = 0; i < NumOps; ++i, ++I) { in UpdateThumbVFPPredicate()
1062 I->setReg(0); in UpdateThumbVFPPredicate()
1081 Size = 0; in getThumbInstruction()
1121 unsigned Firstcond = MI.getOperand(0).getImm(); in getThumbInstruction()
1135 Size = 0; in getThumbInstruction()
1156 unsigned Mask = MI.getOperand(0).getImm(); in getThumbInstruction()
1181 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { in getThumbInstruction()
1198 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { in getThumbInstruction()
1208 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { in getThumbInstruction()
1210 NEONLdStInsn &= 0xF0FFFFFF; in getThumbInstruction()
1211 NEONLdStInsn |= 0x04000000; in getThumbInstruction()
1221 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { in getThumbInstruction()
1223 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 in getThumbInstruction()
1224 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 in getThumbInstruction()
1225 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 in getThumbInstruction()
1235 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 in getThumbInstruction()
1236 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 in getThumbInstruction()
1237 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 in getThumbInstruction()
1246 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 in getThumbInstruction()
1267 Size = 0; in getThumbInstruction()
1293 ARM::R12, 0, ARM::LR, ARM::APSR
1314 if (Register == 0) in DecodeCLRMGPRRegisterClass()
1449 unsigned Register = 0; in DecodetcGPRRegisterClass()
1451 case 0: in DecodetcGPRRegisterClass()
1581 if (RegNo > 31 || (RegNo & 1) != 0) in DecodeQPRRegisterClass()
1636 if (Val == 0xF) return MCDisassembler::Fail; in DecodePredicateOperand()
1638 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) in DecodePredicateOperand()
1646 Inst.addOperand(MCOperand::createReg(0)); in DecodePredicateOperand()
1658 Inst.addOperand(MCOperand::createReg(0)); in DecodeCCOutOperand()
1667 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand()
1677 case 0: in DecodeSORegImmOperand()
1691 if (Shift == ARM_AM::ror && imm == 0) in DecodeSORegImmOperand()
1705 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand()
1717 case 0: in DecodeSORegRegOperand()
1742 unsigned WritebackReg = 0; in DecodeRegListOperand()
1756 WritebackReg = Inst.getOperand(0).getReg(); in DecodeRegListOperand()
1764 if (Val == 0) return MCDisassembler::Fail; in DecodeRegListOperand()
1765 for (unsigned i = 0; i < 16; ++i) { in DecodeRegListOperand()
1790 unsigned regs = fieldFromInstruction(Val, 0, 8); in DecodeSPRRegListOperand()
1793 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1801 for (unsigned i = 0; i < (regs - 1); ++i) { in DecodeSPRRegListOperand()
1818 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1827 for (unsigned i = 0; i < (regs - 1); ++i) { in DecodeDPRRegListOperand()
1844 unsigned lsb = fieldFromInstruction(Val, 0, 5); in DecodeBitfieldMaskOperand()
1855 uint32_t msb_mask = 0xFFFFFFFF; in DecodeBitfieldMaskOperand()
1871 unsigned imm = fieldFromInstruction(Insn, 0, 8); in DecodeCopMemInstruction()
1936 if (coproc == 0xA || coproc == 0xB || in DecodeCopMemInstruction()
1938 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || in DecodeCopMemInstruction()
1939 coproc == 0xE || coproc == 0xF))) in DecodeCopMemInstruction()
2010 // the immediate is unsigned [0,255]. in DecodeCopMemInstruction()
2049 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction()
2050 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeAddrMode2IdxInstruction()
2100 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction()
2101 unsigned idx_mode = 0; in DecodeAddrMode2IdxInstruction()
2115 case 0: in DecodeAddrMode2IdxInstruction()
2131 if (Opc == ARM_AM::ror && amt == 0) in DecodeAddrMode2IdxInstruction()
2137 Inst.addOperand(MCOperand::createReg(0)); in DecodeAddrMode2IdxInstruction()
2154 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand()
2161 case 0: in DecodeSORegMemOperand()
2175 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
2212 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction()
2221 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction()
2231 if (Rt & 0x1) S = MCDisassembler::SoftFail; in DecodeAddrMode3Instruction()
2240 if (P == 0 && W == 1) in DecodeAddrMode3Instruction()
2270 if (P == 0 && W == 1) in DecodeAddrMode3Instruction()
2383 Inst.addOperand(MCOperand::createReg(0)); in DecodeAddrMode3Instruction()
2406 case 0: in DecodeRFEInstruction()
2433 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeQADDInstruction()
2437 if (pred == 0xF) in DecodeQADDInstruction()
2459 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction()
2461 if (pred == 0xF) { in DecodeMemMultipleWritebackInstruction()
2517 if (fieldFromInstruction(Insn, 20, 1) == 0) { in DecodeMemMultipleWritebackInstruction()
2520 fieldFromInstruction(Insn, 20, 1) == 0)) in DecodeMemMultipleWritebackInstruction()
2524 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); in DecodeMemMultipleWritebackInstruction()
2548 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); in DecodeHINTInstruction()
2561 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2573 unsigned mode = fieldFromInstruction(Insn, 0, 5); in DecodeCPSInstruction()
2579 if (fieldFromInstruction(Insn, 5, 1) != 0 || in DecodeCPSInstruction()
2580 fieldFromInstruction(Insn, 16, 1) != 0 || in DecodeCPSInstruction()
2581 fieldFromInstruction(Insn, 20, 8) != 0x10) in DecodeCPSInstruction()
2606 // imod == '00' && M == '0' --> UNPREDICTABLE in DecodeCPSInstruction()
2621 unsigned mode = fieldFromInstruction(Insn, 0, 5); in DecodeT2CPSInstruction()
2647 // imod == '00' && M == '0' --> this is a HINT instruction in DecodeT2CPSInstruction()
2648 int imm = fieldFromInstruction(Insn, 0, 8); in DecodeT2CPSInstruction()
2649 // HINT are defined only for immediate in [0..4] in DecodeT2CPSInstruction()
2661 unsigned imm = fieldFromInstruction(Insn, 0, 8); in DecodeT2HintSpaceInstruction()
2665 if (imm == 0x0D) { in DecodeT2HintSpaceInstruction()
2667 } else if (imm == 0x1D) { in DecodeT2HintSpaceInstruction()
2669 } else if (imm == 0x2D) { in DecodeT2HintSpaceInstruction()
2671 } else if (imm == 0x0F) { in DecodeT2HintSpaceInstruction()
2689 unsigned imm = 0; in DecodeT2MOVTWInstruction()
2691 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); in DecodeT2MOVTWInstruction()
2715 unsigned imm = 0; in DecodeArmMOVTWInstruction()
2717 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); in DecodeArmMOVTWInstruction()
2742 unsigned Rn = fieldFromInstruction(Insn, 0, 4); in DecodeSMLAInstruction()
2747 if (pred == 0xF) in DecodeSMLAInstruction()
2772 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeTSTInstruction()
2774 if (Pred == 0xF) in DecodeTSTInstruction()
2803 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || in DecodeSETPANInstruction()
2804 fieldFromInstruction(Insn, 4,4) != 0) in DecodeSETPANInstruction()
2806 if (fieldFromInstruction(Insn, 10,10) != 0 || in DecodeSETPANInstruction()
2807 fieldFromInstruction(Insn, 0,4) != 0) in DecodeSETPANInstruction()
2822 unsigned imm = fieldFromInstruction(Val, 0, 12); in DecodeAddrModeImm12Operand()
2829 if (imm == 0 && !add) imm = INT32_MIN; in DecodeAddrModeImm12Operand()
2843 // U == 1 to add imm, 0 to subtract it. in DecodeAddrMode5Operand()
2845 unsigned imm = fieldFromInstruction(Val, 0, 8); in DecodeAddrMode5Operand()
2864 // U == 1 to add imm, 0 to subtract it. in DecodeAddrMode5FP16Operand()
2866 unsigned imm = fieldFromInstruction(Val, 0, 8); in DecodeAddrMode5FP16Operand()
2895 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); in DecodeT2BInstruction()
2902 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); in DecodeT2BInstruction()
2918 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; in DecodeBranchImmInstruction()
2920 if (pred == 0xF) { in DecodeBranchImmInstruction()
2947 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeAddrMode6Operand()
2953 Inst.addOperand(MCOperand::createImm(0)); in DecodeAddrMode6Operand()
2970 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLDInstruction()
3151 Inst.addOperand(MCOperand::createImm(0)); in DecodeVLDInstruction()
3184 // The fixed offset encodes as Rm == 0xd, so we check for that. in DecodeVLDInstruction()
3185 if (Rm == 0xd) { in DecodeVLDInstruction()
3186 Inst.addOperand(MCOperand::createReg(0)); in DecodeVLDInstruction()
3215 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback in DecodeVLDInstruction()
3216 // variant encodes Rm == 0xf. Anything else is a register offset post- in DecodeVLDInstruction()
3218 if (Rm != 0xD && Rm != 0xF && in DecodeVLDInstruction()
3302 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVSTInstruction()
3356 if (Rm == 0xF) in DecodeVSTInstruction()
3358 Inst.addOperand(MCOperand::createImm(0)); in DecodeVSTInstruction()
3386 if (Rm == 0xD) in DecodeVSTInstruction()
3387 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSTInstruction()
3388 else if (Rm != 0xF) { in DecodeVSTInstruction()
3571 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLD1DupInstruction()
3575 if (size == 0 && align == 1) in DecodeVLD1DupInstruction()
3592 if (Rm != 0xF) { in DecodeVLD1DupInstruction()
3601 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback in DecodeVLD1DupInstruction()
3602 // variant encodes Rm == 0xf. Anything else is a register offset post- in DecodeVLD1DupInstruction()
3604 if (Rm != 0xD && Rm != 0xF && in DecodeVLD1DupInstruction()
3619 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLD2DupInstruction()
3645 if (Rm != 0xF) in DecodeVLD2DupInstruction()
3646 Inst.addOperand(MCOperand::createImm(0)); in DecodeVLD2DupInstruction()
3652 if (Rm != 0xD && Rm != 0xF) { in DecodeVLD2DupInstruction()
3668 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLD3DupInstruction()
3677 if (Rm != 0xF) { in DecodeVLD3DupInstruction()
3684 Inst.addOperand(MCOperand::createImm(0)); in DecodeVLD3DupInstruction()
3686 if (Rm == 0xD) in DecodeVLD3DupInstruction()
3687 Inst.addOperand(MCOperand::createReg(0)); in DecodeVLD3DupInstruction()
3688 else if (Rm != 0xF) { in DecodeVLD3DupInstruction()
3704 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLD4DupInstruction()
3709 if (size == 0x3) { in DecodeVLD4DupInstruction()
3710 if (align == 0) in DecodeVLD4DupInstruction()
3730 if (Rm != 0xF) { in DecodeVLD4DupInstruction()
3739 if (Rm == 0xD) in DecodeVLD4DupInstruction()
3740 Inst.addOperand(MCOperand::createReg(0)); in DecodeVLD4DupInstruction()
3741 else if (Rm != 0xF) { in DecodeVLD4DupInstruction()
3756 unsigned imm = fieldFromInstruction(Insn, 0, 4); in DecodeVMOVModImmInstruction()
3803 unsigned imm = fieldFromInstruction(Insn, 0, 4); in DecodeMVEModImmInstruction()
3809 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) in DecodeMVEModImmInstruction()
3818 Inst.addOperand(MCOperand::createReg(0)); in DecodeMVEModImmInstruction()
3819 Inst.addOperand(MCOperand::createImm(0)); in DecodeMVEModImmInstruction()
3857 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVSHLMaxInstruction()
3907 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeTBLInstruction()
3941 unsigned imm = fieldFromInstruction(Insn, 0, 8); in DecodeThumbAddSpecialReg()
3992 unsigned Rn = fieldFromInstruction(Val, 0, 3); in DecodeThumbAddrModeRR()
4008 unsigned Rn = fieldFromInstruction(Val, 0, 3); in DecodeThumbAddrModeIS()
4045 unsigned imm = fieldFromInstruction(Val, 0, 2); in DecodeT2AddrModeSOReg()
4144 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; in DecodeT2LoadShift()
4160 unsigned imm = fieldFromInstruction(Insn, 0, 8); in DecodeT2LoadImm8()
4244 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeT2LoadImm12()
4324 unsigned imm = fieldFromInstruction(Insn, 0, 8); in DecodeT2LoadT()
4364 int imm = fieldFromInstruction(Insn, 0, 12); in DecodeT2LoadLabel()
4400 // Special case for #-0. in DecodeT2LoadLabel()
4401 if (imm == 0) in DecodeT2LoadLabel()
4413 if (Val == 0) in DecodeT2Imm8S4()
4416 int imm = Val & 0xFF; in DecodeT2Imm8S4()
4418 if (!(Val & 0x100)) imm *= -1; in DecodeT2Imm8S4()
4427 if (Val == 0) in DecodeT2Imm7S4()
4430 int imm = Val & 0x7F; in DecodeT2Imm7S4()
4432 if (!(Val & 0x80)) in DecodeT2Imm7S4()
4446 unsigned imm = fieldFromInstruction(Val, 0, 9); in DecodeT2AddrModeImm8s4()
4462 unsigned imm = fieldFromInstruction(Val, 0, 8); in DecodeT2AddrModeImm7s4()
4478 unsigned imm = fieldFromInstruction(Val, 0, 8); in DecodeT2AddrModeImm0_1020s4()
4490 int imm = Val & 0xFF; in DecodeT2Imm8()
4491 if (Val == 0) in DecodeT2Imm8()
4493 else if (!(Val & 0x100)) in DecodeT2Imm8()
4503 int imm = Val & 0x7F; in DecodeT2Imm7()
4504 if (Val == 0) in DecodeT2Imm7()
4506 else if (!(Val & 0x80)) in DecodeT2Imm7()
4521 unsigned imm = fieldFromInstruction(Val, 0, 9); in DecodeT2AddrModeImm8()
4548 imm |= 0x100; in DecodeT2AddrModeImm8()
4569 unsigned imm = fieldFromInstruction(Val, 0, 8); in DecodeTAddrModeImm7()
4586 unsigned imm = fieldFromInstruction(Val, 0, 8); in DecodeT2AddrModeImm7()
4605 unsigned addr = fieldFromInstruction(Insn, 0, 8); in DecodeT2LdStPre()
4666 unsigned imm = fieldFromInstruction(Val, 0, 12); in DecodeT2AddrModeImm12()
4690 unsigned imm = fieldFromInstruction(Insn, 0, 7); in DecodeThumbAddSPImm()
4705 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); in DecodeThumbAddSPReg()
4728 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; in DecodeThumbCPS()
4729 unsigned flags = fieldFromInstruction(Insn, 0, 3); in DecodeThumbCPS()
4741 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodePostIdxReg()
4756 unsigned Qm = fieldFromInstruction(Insn, 0, 3); in DecodeMveAddrModeRQ()
4772 int imm = fieldFromInstruction(Insn, 0, 7); in DecodeMveAddrModeQ()
4778 if (imm == 0) in DecodeMveAddrModeQ()
4779 imm = INT32_MIN; // indicate -0 in DecodeMveAddrModeQ()
4793 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' in DecodeThumbBLXOffset()
4805 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); in DecodeThumbBLXOffset()
4818 if (Val == 0xA || Val == 0xB) in DecodeCoprocessor()
4839 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeThumbTableBranch()
4855 if (pred == 0xE || pred == 0xF) { in DecodeThumb2BCCInstruction()
4860 case 0xf3bf8f4: in DecodeThumb2BCCInstruction()
4863 case 0xf3bf8f5: in DecodeThumb2BCCInstruction()
4866 case 0xf3bf8f6: in DecodeThumb2BCCInstruction()
4871 unsigned imm = fieldFromInstruction(Insn, 0, 4); in DecodeThumb2BCCInstruction()
4875 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; in DecodeThumb2BCCInstruction()
4895 if (ctrl == 0) { in DecodeT2SOImm()
4897 unsigned imm = fieldFromInstruction(Val, 0, 8); in DecodeT2SOImm()
4899 case 0: in DecodeT2SOImm()
4914 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; in DecodeT2SOImm()
4941 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); in DecodeThumbBLTargetOperand()
4947 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); in DecodeThumbBLTargetOperand()
4959 if (Val & ~0xf) in DecodeMemBarrierOption()
4969 if (Val & ~0xf) in DecodeInstSyncBarrierOption()
4983 unsigned ValLow = Val & 0xff; in DecodeMSRMask()
4987 case 0: // apsr in DecodeMSRMask()
5006 case 0x8a: // msplim_ns in DecodeMSRMask()
5007 case 0x8b: // psplim_ns in DecodeMSRMask()
5008 case 0x91: // basepri_ns in DecodeMSRMask()
5009 case 0x93: // faultmask_ns in DecodeMSRMask()
5015 case 0x88: // msp_ns in DecodeMSRMask()
5016 case 0x89: // psp_ns in DecodeMSRMask()
5017 case 0x90: // primask_ns in DecodeMSRMask()
5018 case 0x94: // control_ns in DecodeMSRMask()
5019 case 0x98: // sp_ns in DecodeMSRMask()
5023 case 0x20: // pac_key_p_0 in DecodeMSRMask()
5024 case 0x21: // pac_key_p_1 in DecodeMSRMask()
5025 case 0x22: // pac_key_p_2 in DecodeMSRMask()
5026 case 0x23: // pac_key_p_3 in DecodeMSRMask()
5027 case 0x24: // pac_key_u_0 in DecodeMSRMask()
5028 case 0x25: // pac_key_u_1 in DecodeMSRMask()
5029 case 0x26: // pac_key_u_2 in DecodeMSRMask()
5030 case 0x27: // pac_key_u_3 in DecodeMSRMask()
5031 case 0xa0: // pac_key_p_0_ns in DecodeMSRMask()
5032 case 0xa1: // pac_key_p_1_ns in DecodeMSRMask()
5033 case 0xa2: // pac_key_p_2_ns in DecodeMSRMask()
5034 case 0xa3: // pac_key_p_3_ns in DecodeMSRMask()
5035 case 0xa4: // pac_key_u_0_ns in DecodeMSRMask()
5036 case 0xa5: // pac_key_u_1_ns in DecodeMSRMask()
5037 case 0xa6: // pac_key_u_2_ns in DecodeMSRMask()
5038 case 0xa7: // pac_key_u_3_ns in DecodeMSRMask()
5051 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are in DecodeMSRMask()
5059 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if in DecodeMSRMask()
5060 // the NZCVQ bits should be moved by the instruction. Bit mask{0} in DecodeMSRMask()
5061 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set in DecodeMSRMask()
5063 if (Mask == 0 || (Mask != 2 && ValLow > 3) || in DecodeMSRMask()
5070 if (Val == 0) in DecodeMSRMask()
5081 unsigned SysM = fieldFromInstruction(Val, 0, 5); in DecodeBankedReg()
5102 if (Rn == 0xF) in DecodeDoubleRegLoad()
5121 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeDoubleRegStore()
5128 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) in DecodeDoubleRegStore()
5148 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeLDRPreImm()
5153 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; in DecodeLDRPreImm()
5174 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeLDRPreReg()
5178 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeLDRPreReg()
5180 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; in DecodeLDRPreReg()
5181 if (Rm == 0xF) S = MCDisassembler::SoftFail; in DecodeLDRPreReg()
5202 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeSTRPreImm()
5207 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; in DecodeSTRPreImm()
5228 unsigned imm = fieldFromInstruction(Insn, 0, 12); in DecodeSTRPreReg()
5233 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; in DecodeSTRPreReg()
5252 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLD1LN()
5257 unsigned align = 0; in DecodeVLD1LN()
5258 unsigned index = 0; in DecodeVLD1LN()
5262 case 0: in DecodeVLD1LN()
5280 case 0 : in DecodeVLD1LN()
5281 align = 0; break; in DecodeVLD1LN()
5292 if (Rm != 0xF) { // Writeback in DecodeVLD1LN()
5299 if (Rm != 0xF) { in DecodeVLD1LN()
5300 if (Rm != 0xD) { in DecodeVLD1LN()
5304 Inst.addOperand(MCOperand::createReg(0)); in DecodeVLD1LN()
5319 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVST1LN()
5324 unsigned align = 0; in DecodeVST1LN()
5325 unsigned index = 0; in DecodeVST1LN()
5329 case 0: in DecodeVST1LN()
5347 case 0: in DecodeVST1LN()
5348 align = 0; break; in DecodeVST1LN()
5357 if (Rm != 0xF) { // Writeback in DecodeVST1LN()
5364 if (Rm != 0xF) { in DecodeVST1LN()
5365 if (Rm != 0xD) { in DecodeVST1LN()
5369 Inst.addOperand(MCOperand::createReg(0)); in DecodeVST1LN()
5384 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLD2LN()
5389 unsigned align = 0; in DecodeVLD2LN()
5390 unsigned index = 0; in DecodeVLD2LN()
5395 case 0: in DecodeVLD2LN()
5411 if (fieldFromInstruction(Insn, 4, 1) != 0) in DecodeVLD2LN()
5422 if (Rm != 0xF) { // Writeback in DecodeVLD2LN()
5429 if (Rm != 0xF) { in DecodeVLD2LN()
5430 if (Rm != 0xD) { in DecodeVLD2LN()
5434 Inst.addOperand(MCOperand::createReg(0)); in DecodeVLD2LN()
5451 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVST2LN()
5456 unsigned align = 0; in DecodeVST2LN()
5457 unsigned index = 0; in DecodeVST2LN()
5462 case 0: in DecodeVST2LN()
5478 if (fieldFromInstruction(Insn, 4, 1) != 0) in DecodeVST2LN()
5485 if (Rm != 0xF) { // Writeback in DecodeVST2LN()
5492 if (Rm != 0xF) { in DecodeVST2LN()
5493 if (Rm != 0xD) { in DecodeVST2LN()
5497 Inst.addOperand(MCOperand::createReg(0)); in DecodeVST2LN()
5514 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLD3LN()
5519 unsigned align = 0; in DecodeVLD3LN()
5520 unsigned index = 0; in DecodeVLD3LN()
5525 case 0: in DecodeVLD3LN()
5553 if (Rm != 0xF) { // Writeback in DecodeVLD3LN()
5560 if (Rm != 0xF) { in DecodeVLD3LN()
5561 if (Rm != 0xD) { in DecodeVLD3LN()
5565 Inst.addOperand(MCOperand::createReg(0)); in DecodeVLD3LN()
5584 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVST3LN()
5589 unsigned align = 0; in DecodeVST3LN()
5590 unsigned index = 0; in DecodeVST3LN()
5595 case 0: in DecodeVST3LN()
5616 if (Rm != 0xF) { // Writeback in DecodeVST3LN()
5623 if (Rm != 0xF) { in DecodeVST3LN()
5624 if (Rm != 0xD) { in DecodeVST3LN()
5628 Inst.addOperand(MCOperand::createReg(0)); in DecodeVST3LN()
5647 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVLD4LN()
5652 unsigned align = 0; in DecodeVLD4LN()
5653 unsigned index = 0; in DecodeVLD4LN()
5658 case 0: in DecodeVLD4LN()
5672 case 0: in DecodeVLD4LN()
5673 align = 0; break; in DecodeVLD4LN()
5695 if (Rm != 0xF) { // Writeback in DecodeVLD4LN()
5702 if (Rm != 0xF) { in DecodeVLD4LN()
5703 if (Rm != 0xD) { in DecodeVLD4LN()
5707 Inst.addOperand(MCOperand::createReg(0)); in DecodeVLD4LN()
5728 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeVST4LN()
5733 unsigned align = 0; in DecodeVST4LN()
5734 unsigned index = 0; in DecodeVST4LN()
5739 case 0: in DecodeVST4LN()
5753 case 0: in DecodeVST4LN()
5754 align = 0; break; in DecodeVST4LN()
5767 if (Rm != 0xF) { // Writeback in DecodeVST4LN()
5774 if (Rm != 0xF) { in DecodeVST4LN()
5775 if (Rm != 0xD) { in DecodeVST4LN()
5779 Inst.addOperand(MCOperand::createReg(0)); in DecodeVST4LN()
5802 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; in DecodeVMOVSRR()
5804 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
5828 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; in DecodeVMOVRRS()
5830 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVRRS()
5851 unsigned mask = fieldFromInstruction(Insn, 0, 4); in DecodeIT()
5853 if (pred == 0xF) { in DecodeIT()
5854 pred = 0xE; in DecodeIT()
5858 if (mask == 0x0) in DecodeIT()
5867 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); in DecodeIT()
5884 unsigned addr = fieldFromInstruction(Insn, 0, 8); in DecodeT2LDRDPreInstruction()
5888 bool writeback = (W == 1) | (P == 0); in DecodeT2LDRDPreInstruction()
5921 unsigned addr = fieldFromInstruction(Insn, 0, 8); in DecodeT2STRDPreInstruction()
5925 bool writeback = (W == 1) | (P == 0); in DecodeT2STRDPreInstruction()
5954 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); in DecodeT2Adr()
5957 unsigned Val = fieldFromInstruction(Insn, 0, 8); in DecodeT2Adr()
5980 if (Val == 0x20) S = MCDisassembler::Fail; in DecodeT2ShifterImmOperand()
5988 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); in DecodeSwap()
5992 if (pred == 0xF) in DecodeSwap()
6018 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTD()
6020 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTD()
6029 if (!(imm & 0x38)) { in DecodeVCVTD()
6030 if (cmode == 0xF) { in DecodeVCVTD()
6035 if (cmode == 0xE) { in DecodeVCVTD()
6042 if (cmode == 0xD) { in DecodeVCVTD()
6049 if (cmode == 0xC) { in DecodeVCVTD()
6060 if (!(imm & 0x20)) return MCDisassembler::Fail; in DecodeVCVTD()
6077 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTQ()
6079 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTQ()
6088 if (!(imm & 0x38)) { in DecodeVCVTQ()
6089 if (cmode == 0xF) { in DecodeVCVTQ()
6094 if (cmode == 0xE) { in DecodeVCVTQ()
6101 if (cmode == 0xD) { in DecodeVCVTQ()
6108 if (cmode == 0xC) { in DecodeVCVTQ()
6119 if (!(imm & 0x20)) return MCDisassembler::Fail; in DecodeVCVTQ()
6134 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeNEONComplexLane64Instruction()
6136 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); in DecodeNEONComplexLane64Instruction()
6138 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeNEONComplexLane64Instruction()
6140 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); in DecodeNEONComplexLane64Instruction()
6141 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); in DecodeNEONComplexLane64Instruction()
6156 // be 0. in DecodeNEONComplexLane64Instruction()
6157 Inst.addOperand(MCOperand::createImm(0)); in DecodeNEONComplexLane64Instruction()
6169 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeLDR()
6173 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) in DecodeLDR()
6195 unsigned CRm = fieldFromInstruction(Val, 0, 4); in DecoderForMRRC2AndMCRR2()
6201 if ((cop & ~0x1) == 0xa) in DecoderForMRRC2AndMCRR2()
6277 Inst.addOperand(MCOperand::createReg(0)); in DecodeForVMRSandVMSR()
6292 if (Val == 0 && !zeroPermitted) in DecodeBFLabelOperand()
6311 uint64_t LocImm = Inst.getOperand(0).getImm(); in DecodeBFAfterTargetOperand()
6367 if (Rn == 0xF) { in DecodeLOLoop()
6371 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; in DecodeLOLoop()
6395 if (Val == 0) in DecodeLongShiftOperand()
6448 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSCCLRM()
6457 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | in DecodeVSCCLRM()
6519 // 't' as 0 and finish with a 1. in DecodeVPTMaskOperand()
6520 unsigned Imm = 0; in DecodeVPTMaskOperand()
6522 unsigned CurBit = 0; in DecodeVPTMaskOperand()
6523 for (int i = 3; i >= 0; --i) { in DecodeVPTMaskOperand()
6532 if ((Val & ~(~0U << i)) == 0) { in DecodeVPTMaskOperand()
6570 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); in DecodeRestrictedIPredicateOperand()
6578 switch (Val & 0x3) { in DecodeRestrictedSPredicateOperand()
6579 case 0: in DecodeRestrictedSPredicateOperand()
6599 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); in DecodeRestrictedUPredicateOperand()
6610 case 0: in DecodeRestrictedFPPredicateOperand()
6673 return 0; in FixedRegForVSTRVLDR_SYSREG()
6705 unsigned addr = fieldFromInstruction(Val, 0, 7) | in DecodeVSTRVLDR_SYSREG()
6716 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSTRVLDR_SYSREG()
6728 unsigned addr = fieldFromInstruction(Val, 0, 7) | in DecodeMVE_MEM_pre()
6799 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeMVEVMOVQtoDReg()
6813 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) in DecodeMVEVMOVQtoDReg()
6823 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeMVEVMOVDRegtoQ()
6839 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) in DecodeMVEVMOVDRegtoQ()
6960 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeMVEVCMP()
6966 fieldFromInstruction(Insn, 0, 1) << 1; in DecodeMVEVCMP()
6977 Inst.addOperand(MCOperand::createReg(0)); in DecodeMVEVCMP()
6978 Inst.addOperand(MCOperand::createImm(0)); in DecodeMVEVCMP()
7009 fieldFromInstruction(Insn, 0, 8); in DecodeT2AddSubSPImm()
7052 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect. in DecodeLazyLoadStoreMul()