165   // ABIs other than APCS have 64 bit integers with natural alignment.  in computeDataLayout()
167     Ret += "-i64:64";  in computeDataLayout()
169   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32  in computeDataLayout()
170   // bits, others to 64 bits. We always try to align to 64 bits.  in computeDataLayout()
172     Ret += "-f64:32:64";  in computeDataLayout()
174   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others  in computeDataLayout()
175   // to 64. We always ty to give them natural alignment.  in computeDataLayout()
177     Ret += "-v64:32:64-v128:32:128";  in computeDataLayout()
179     Ret += "-v128:64:128";  in computeDataLayout()
181   // Try to align aggregates to 32 bits (the default is 64 bits, which has no  in computeDataLayout()
188   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit  in computeDataLayout()
220                                            StringRef CPU, StringRef FS,  in ARMBaseTargetMachine()  argument
226                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),  in ARMBaseTargetMachine()
287   std::string FS =  in getSubtargetImpl()  local
299     FS += FS.empty() ? "+soft-float" : ",+soft-float";  in getSubtargetImpl()
303   std::string Key = CPU + FS;  in getSubtargetImpl()
313     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,  in getSubtargetImpl()
330                                        StringRef CPU, StringRef FS,  in ARMLETargetMachine()  argument
335     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}  in ARMLETargetMachine()
338                                        StringRef CPU, StringRef FS,  in ARMBETargetMachine()  argument
343     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}  in ARMBETargetMachine()