Lines Matching +full:pre +full:- +full:multiply
1 //=- ARMScheduleSwift.td - Swift Scheduling Definitions -*- tablegen -*----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
31 // FIXME: Do we need to model the fact that uses of r15 in a micro-op force it
34 // FIXME: Better model the microcode stages of multiply instructions, especially
37 // FIXME: Model non-pipelined nature of FP div / sqrt unit.
41 let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
52 def IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>;
104 foreach Num = 1-4 in {
155 // MOV(register-shiftedregister) MVN(register-shiftedregister)
220 // 4.2.12 Integer Multiply (32-bit result)
243 // Multiply accumulate, three sources
250 // 4.2.13 Integer Multiply (32-bit result, Q flag)
279 // 4.2.14 Integer Multiply, Long
289 // Aliasing sub-target specific WriteRes to generic ones
301 // 4.2.15 Integer Multiply Accumulate, Long
302 // 4.2.16 Integer Multiply Accumulate, Dual
303 // 4.2.17 Integer Multiply Accumulate Accumulate, Long
366 (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
368 "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>;
378 (instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>;
382 foreach Lat = 3-25 in {
392 foreach NumAddr = 1-16 in {
393 def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == "#NumAddr>;
496 "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)",
497 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
505 (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>;
512 foreach NumAddr = 1-16 in {
585 foreach Num = 1-4 in {
612 // 4.2.35 Advanced SIMD and VFP, Multiply
683 foreach Num = 1-28 in {
691 // Pre RA pseudos - load/store to a Q register as a D register pair.
715 // Load of 3 D registers. (Must also be able to handle s register list -
869 foreach Num = 1-2 in {
1051 // ===---------------------------------------------------------------------===//
1052 // Floating-point. Map target defined SchedReadWrite to processor specific ones