Lines Matching +full:spi +full:- +full:crc
1 //==- ARMScheduleR52.td - Cortex-R52 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the SchedRead/Write data for the ARM Cortex-R52 processor.
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
14 // The Cortex-R52 is an in-order pipelined superscalar microprocessor with
16 // There are two ALUs, one LDST, one MUL and a non-pipelined integer DIV.
22 let MicroOpBufferSize = 0; // R52 is in-order processor
23 let IssueWidth = 2; // 2 micro-ops dispatched per cycle
26 let CompleteModel = 0; // Covers instructions applicable to cortex-r52.
30 //===----------------------------------------------------------------------===//
34 // Cortex-R52 is an in-order processor.
45 // Cortex-R52 specific SchedReads
55 //===----------------------------------------------------------------------===//
56 // Subtarget-specific SchedWrite types which map ProcResources and set latency.
60 // ALU - Write occurs in Late EX2 (independent of whether shift was required)
71 // Multiply - aliased to sub-target specific later
73 // Div - may stall 0-9 cycles depending on input (i.e. WRI+(0-9)/2)
75 let Latency = 8; let ReleaseAtCycles = [8]; // non-pipelined
78 // Branches - LR written in Late EX2
86 // Integer pipeline by-passes
92 // Floating-point. Map target-defined SchedReadWrites to subtarget
128 def : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1
130 //===----------------------------------------------------------------------===//
131 // Subtarget-specific SchedReadWrites.
133 // Forwarding information - based on when an operand is read
142 // Cortex-R52 specific SchedWrites for use with InstRW
161 // Alias generics to sub-target specific
201 //===----------------------------------------------------------------------===//
202 // Floating-point. Map target defined SchedReadWrites to processor specific ones
209 //===----------------------------------------------------------------------===//
210 // Subtarget-specific overrides. Map opcodes to list of SchedReadWrites types.
268 // Even for 64-bit accumulation (or Long), the single MAC is used (not ALUs).
269 // The store pipeline is used partly for 64-bit operations.
289 // However, that's non-trivial to specify, so we keep it uniform
293 "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)",
314 "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr",
346 foreach Lat = 3-25 in {
355 foreach NAddr = 1-16 in {
356 def R52ILDMAddr#NAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == "#NAddr>;
456 foreach NumAddr = 1-16 in {
519 //===----------------------------------------------------------------------===//
538 //===----------------------------------------------------------------------===//
542 foreach NumAddr = 1-16 in {
544 SchedPredicate<"MI->getNumOperands() == "#NumAddr>;
546 foreach Lat = 1-32 in {
551 foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
638 // variable stores. Cannot dual-issue
716 // Vector Load/Stores. Can issue only in slot-0. Can dual-issue with
717 // another instruction in slot-1, but only in the last issue.
832 //---
834 //---
835 // 1-element structure store
858 // 2-element structure store
881 // 3-element structure store
904 // 4-element structure store