Lines Matching +full:pre +full:- +full:multiply
1 //=- ARMScheduleM7.td - ARM Cortex-M7 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
11 //===----------------------------------------------------------------------===//
15 let MicroOpBufferSize = 0; // The Cortex-M7 is in-order.
16 let LoadLatency = 2; // Best case for load-use case.
24 //===--------------------------------------------------------------------===//
25 // The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
53 //===---------------------------------------------------------------------===//
54 // Subtarget-specific SchedWrite types with map ProcResources and set latency.
78 // Multiply-accumulates.
87 // These cannot be dual-issued with any instructions.
106 //===---------------------------------------------------------------------===//
107 // Sched definitions for floating-point instructions
117 // ALU operations (32/64-bit). These go down the FP pipeline.
131 // Multiply-accumulate. FPMAC goes down the FP Pipeline.
145 // Square-root. Effective scheduling latency is 3; real latency is larger
181 def M7Read_ISS : SchedReadAdvance<-1>; // operands needed at EX1
200 //===---------------------------------------------------------------------===//
203 // Mark whether the loads/stores must be single-issue
217 // Byte and half-word loads should have greater latency than other loads.
228 (instregex "t2LDR(B|H|SB|SH)_(POST|PRE)")>;
230 // Exclusive loads/stores cannot be dual-issued
238 // Load/store multiples cannot be dual-issued. Note that default scheduling
251 // Load/store doubles cannot be dual-issued.
255 (instregex "t2STRD_(PRE|POST)")>;
259 (instregex "t2LDRD_(PRE|POST)")>;
271 (instregex "t2LDR_(POST|PRE)")>;
275 (instregex "t2STR(B|H)?_(POST|PRE)")>;
281 // TBB/TBH - single-issue only; takes two cycles to issue
307 // Load/store multiples cannot be dual-issued.
318 //===---------------------------------------------------------------------===//
323 def M7Ex1ReadNoFastBypass : SchedReadAdvance<-1, [WriteLd, M7LoadLatency1]>;
334 // can choose the EX2 shifter when needed. Will miss a few dual-issue cases,
353 // single-cycle as far as scheduling opportunities go. By putting WriteALU
404 //===---------------------------------------------------------------------===//
457 // Larger-latency overrides.
468 // Multiply-accumulate. Chained SP timing is correct; rest need overrides
469 // Double-precision chained MAC stalls the pipeline behind it for 3 cycles,
476 // Single-precision fused MACs look like latency 5 with advance of 2.
488 // Double-precision fused MAC stalls the pipeline behind it for 2 cycles, making