Lines Matching +full:low +full:- +full:latency

1 //===-- ARMSchedule.td - ARM Scheduling Definitions --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
8 //===----------------------------------------------------------------------===//
9 // Instruction scheduling annotations for in-order and out-of-order CPUs.
11 // Here we define the subtarget independent read/write per-operand resources.
17 // Rd <- ADD Rn, Rm, <shift> Rs
18 //  Uops | Latency from register | Uops - resource requirements - latency
19 //  2    | Rn: 1 Rm: 4 Rs: 4     | uop T0, Rm, Rs - P01 - 3
20 //       |                       | uopc Rd, Rn, T0 -  P01 - 1
23 // and one cycle after the result in Rn is available. The micro-ops can execute
25 // To model this, we need to express that we need to dispatch two micro-ops,
26 // that the resource P01 is needed and that the latency to Rn is different than
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
37 // ReadAdvance read resources allow us to define "pipeline by-passes" or
48 //    Latency = 4; // Latency of 4.
49 //    NumMicroOps = 2; // Dispatch 2 micro-ops.
56 //===----------------------------------------------------------------------===//
75 def WriteMUL16   : SchedWrite; // 16-bit multiply.
76 def WriteMUL32   : SchedWrite; // 32-bit multiply.
77 def WriteMUL64Lo : SchedWrite; // 64-bit result. Low reg.
78 def WriteMUL64Hi : SchedWrite; // 64-bit result. High reg.
81 // Multiply-accumulates.
82 def WriteMAC16   : SchedWrite; // 16-bit mac.
83 def WriteMAC32   : SchedWrite; // 32-bit mac.
84 def WriteMAC64Lo : SchedWrite; // 64-bit mac. Low reg.
85 def WriteMAC64Hi : SchedWrite; // 64-bit mac. High reg.
104 //===----------------------------------------------------------------------===//
105 // Sched definitions for floating-point and neon instructions
109 def WriteFPMOV : SchedWrite; // FP -> GPR and vice-versa
111 // ALU operations (32/64-bit)
121 // Multiply-accumulate
129 // Square-root
147     static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
150     static_cast<const ARMSubtarget*>(SchedModel->getSubtargetInfo());
197   let Latency = !add(wr.Latency, lat);
209 //===----------------------------------------------------------------------===//