Lines Matching +full:non +full:- +full:pc
1 //===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 // Registers are identified with 4-bit ID numbers.
21 // All bits of ARM registers with sub-registers are covered by sub-registers.
87 // These require 32-bit instructions.
97 def PC : ARMReg<15, "pc", [], ["r15"]>, DwarfRegNum<[15]>;
119 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
157 // Advanced SIMD (NEON) defines 16 quad-word aliases
183 // it has the same encoding as PC.
194 // Special Registers - only available in privileged mode.
218 // pc == Program Counter
222 // r7 == Frame Pointer (thumb-style backtraces)
224 // r11 == Frame Pointer (arm-style backtraces)
228 SP, LR, PC)> {
243 // This is used for pseudo-instructions that are actually implemented using a
259 // GPRs without the PC. Some ARM instructions do not allow the PC in
262 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
271 // GPRs without the PC but with APSR. Some instructions allow accessing the
272 // APSR, while actually encoding PC in the register field. This is useful
274 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
283 def GPRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, PC)> {
289 let DiagnosticString = "operand must be a register in range [r0, r12] or LR or PC";
292 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
297 def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> {
313 // GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the
322 // GPRlr - Only LR is legal. Used by ARMv8.1-M Low Overhead Loop instructions
327 // register range for operands, but have undefined behaviours when PC
329 // via the BadReg() pseudo-code description.
330 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
339 // GPRs without the PC and SP but with APSR_NZCV.Some instructions allow
340 // accessing the APSR_NZCV, while actually encoding PC in the register field.
350 // Thumb registers are R0-R7 normally. Some instructions can still use
356 // Thumb registers R0-R7 and the PC. Some instructions like TBB or THH allow
357 // the PC to be used as a destination operand as well.
358 def tGPRwithpc : RegisterClass<"ARM", [i32], 32, (add tGPR, PC)>;
360 // The high registers in thumb mode, R8-R15.
365 // For tail calls, we can't use callee-saved registers, as they are restored
392 "operand must be an odd-numbered register in range [r1,r11]";
400 let DiagnosticString = "operand must be an even-numbered register";
405 let CopyCost = -1; // Don't allow copying of status registers.
411 // let CopyCost = -1; // Don't allow copying of status registers.
420 // to avoid partial-write dependencies on D or Q (depending on platform)
446 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
452 // Scalar double precision floating point / generic 64-bit vector register
455 // is double-word alignment though.
458 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on
476 // 32-bit SPR subregs).
482 // Subset of DPR which can be used as a source of NEON scalars for 16-bit
489 // Generic 128-bit vector register class.
492 // Allocate non-VFP2 aliases Q8-Q15 first.
500 // Subset of QPR that have 32-bit SPR subregs.
512 // MVE 128-bit vector register class. This class is only really needed for
518 // Pseudo-registers representing odd-even pairs of D registers. The even-odd
527 // Use the Q registers for the even-odd pairs.
530 // Allocate starting at non-VFP2 registers D16-D31 first.
531 // Prefer even-odd pairs as they are easier to copy.
539 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
540 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
548 // Register class representing a pair of even-odd GPRs.
553 // Register class representing a pair of even-odd GPRs, except (R12, SP).
558 // Pseudo-registers representing 3 consecutive D registers.
569 // Pseudo 256-bit registers to represent pairs of Q registers. These should
574 // Pseudo 256-bit vector register class to model pairs of Q registers
577 // Allocate non-VFP2 aliases first.
582 // Same as QQPR but for MVE, containing the 7 register pairs made up from Q0-Q7.
596 // Pseudo 512-bit registers to represent four consecutive Q registers.
600 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
603 // Allocate non-VFP2 aliases first.
608 // Same as QQPR but for MVE, containing the 5 register quads made up from Q0-Q7.
612 // Pseudo-registers representing 2-spaced consecutive D registers.