59   using MemInstList = SmallVectorImpl<LoadInst*>;
70     SmallVector<LoadInst*, 2> VecLd;    // Container for loads to widen.
76       return isa<LoadInst>(LHS) && isa<LoadInst>(RHS);  in HasTwoLoadInputs()
79     LoadInst *getBaseLoad() const {  in getBaseLoad()
196     LoadInst *NewLd = nullptr;
197     SmallVector<LoadInst*, 4> Loads;
200     WidenedLoad(SmallVectorImpl<LoadInst*> &Lds, LoadInst *Wide)  in WidenedLoad()
204     LoadInst *getLoad() {  in getLoad()
216     std::map<LoadInst*, LoadInst*> LoadPairs;
217     SmallPtrSet<LoadInst*, 4> OffsetLoads;
218     std::map<LoadInst*, std::unique_ptr<WidenedLoad>> WideLoads;
225     bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
226     LoadInst* CreateWideLoad(MemInstList &Loads, IntegerType *LoadTy);
299 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1,  in AreSequentialLoads()
329     if (auto *Ld = dyn_cast<LoadInst>(SExt->getOperand(0))) {  in IsNarrowSequence()
340   SmallVector<LoadInst*, 8> Loads;  in RecordMemoryOps()
351     auto *Ld = dyn_cast<LoadInst>(&I);  in RecordMemoryOps()
381   auto SafeToPair = [&](LoadInst *Base, LoadInst *Offset) {  in RecordMemoryOps()
383     LoadInst *Dominator = BaseFirst ? Base : Offset;  in RecordMemoryOps()
384     LoadInst *Dominated = BaseFirst ? Offset : Base;  in RecordMemoryOps()
562     auto Ld0 = static_cast<LoadInst*>(PMul0->LHS);  in CreateParallelPairs()
563     auto Ld1 = static_cast<LoadInst*>(PMul1->LHS);  in CreateParallelPairs()
564     auto Ld2 = static_cast<LoadInst*>(PMul0->RHS);  in CreateParallelPairs()
565     auto Ld3 = static_cast<LoadInst*>(PMul1->RHS);  in CreateParallelPairs()
625   auto CreateSMLAD = [&](LoadInst* WideLd0, LoadInst *WideLd1,  in InsertParallelMACs()
715     LoadInst *BaseLHS = LHSMul->getBaseLoad();  in InsertParallelMACs()
716     LoadInst *BaseRHS = RHSMul->getBaseLoad();  in InsertParallelMACs()
717     LoadInst *WideLHS = WideLoads.count(BaseLHS) ?  in InsertParallelMACs()
719     LoadInst *WideRHS = WideLoads.count(BaseRHS) ?  in InsertParallelMACs()
729 LoadInst* ARMParallelDSP::CreateWideLoad(MemInstList &Loads,  in CreateWideLoad()
733   LoadInst *Base = Loads[0];  in CreateWideLoad()
734   LoadInst *Offset = Loads[1];  in CreateWideLoad()
761   LoadInst *DomLoad = DT->dominates(Base, Offset) ? Base : Offset;  in CreateWideLoad()
769   LoadInst *WideLoad = IRB.CreateAlignedLoad(LoadTy, VecPtr, Base->getAlign());  in CreateWideLoad()