Lines Matching full:ld0
225 bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
299 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, in AreSequentialLoads() argument
301 if (!Ld0 || !Ld1) in AreSequentialLoads()
304 if (!LoadPairs.count(Ld0) || LoadPairs[Ld0] != Ld1) in AreSequentialLoads()
308 dbgs() << "Ld0:"; Ld0->dump(); in AreSequentialLoads()
313 VecMem.push_back(Ld0); in AreSequentialLoads()
481 // ld0 = load i16
482 // sext0 = sext i16 %ld0 to i32
562 auto Ld0 = static_cast<LoadInst*>(PMul0->LHS); in CreateParallelPairs() local
568 if (Ld0 == Ld2 || Ld1 == Ld3) in CreateParallelPairs()
571 if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd)) { in CreateParallelPairs()
582 } else if (AreSequentialLoads(Ld1, Ld0, PMul0->VecLd) && in CreateParallelPairs()
585 LLVM_DEBUG(dbgs() << " exchanging Ld0 and Ld1\n"); in CreateParallelPairs()