1524   bool isLd = isLoadSingle(Opcode);  in MergeBaseUpdateLoadStore()  local
1533                    .addReg(Base, getKillRegState(isLd ? BaseKill : false))  in MergeBaseUpdateLoadStore()
1536                    .addReg(MO.getReg(), (isLd ? getDefRegState(true)  in MergeBaseUpdateLoadStore()
1541   } else if (isLd) {  in MergeBaseUpdateLoadStore()
1789   bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;  in FixInvalidRegPairOp()  local
1790   bool EvenDeadKill = isLd ?  in FixInvalidRegPairOp()
1793   bool OddDeadKill  = isLd ?  in FixInvalidRegPairOp()
1807     unsigned NewOpc = (isLd)  in FixInvalidRegPairOp()
1810     if (isLd) {  in FixInvalidRegPairOp()
1814         .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))  in FixInvalidRegPairOp()
1815         .addReg(OddReg,  getDefRegState(isLd) | getDeadRegState(OddDeadKill))  in FixInvalidRegPairOp()
1831     unsigned NewOpc = (isLd)  in FixInvalidRegPairOp()
1836     unsigned NewOpc2 = (isLd)  in FixInvalidRegPairOp()
1841     if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {  in FixInvalidRegPairOp()
1843       InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,  in FixInvalidRegPairOp()
1845       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,  in FixInvalidRegPairOp()
1859       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,  in FixInvalidRegPairOp()
1862       InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,  in FixInvalidRegPairOp()
1866     if (isLd)  in FixInvalidRegPairOp()
2176         unsigned Base, bool isLd, DenseMap<MachineInstr *, unsigned> &MI2LocMap,
2218 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,  in IsSafeAndProfitableToMove()  argument
2232     if (I->mayStore() || (!isLd && I->mayLoad()))  in IsSafeAndProfitableToMove()
2325     bool isLd, DenseMap<MachineInstr *, unsigned> &MI2LocMap,  in RescheduleOps()  argument
2400         DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,  in RescheduleOps()
2407         MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;  in RescheduleOps()
2435           if (isLd) {  in RescheduleOps()
2475             if (isLd) {  in RescheduleOps()
2571       bool isLd = isLoadSingle(Opc);  in RescheduleLoadStoreInstrs()  local
2592       if (isLd)  in RescheduleLoadStoreInstrs()