178         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
184         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
630     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreMulti()  argument
704     int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm  in CreateLoadStoreMulti()
716       BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm  in CreateLoadStoreMulti()
729     bool KillOldBase = BaseKill &&  in CreateLoadStoreMulti()
777     BaseKill = true; // New base is always killed straight away.  in CreateLoadStoreMulti()
796   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)  in CreateLoadStoreMulti()
813        .addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
817     if (!BaseKill)  in CreateLoadStoreMulti()
822     MIB.addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
837     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreDouble()  argument
907   bool BaseKill = LatestMI->killsRegister(Base, /*TRI=*/nullptr);  in MergeOpsUpdate()  local
913     Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
917     Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
1296   bool BaseKill = BaseOP.isKill();  in MergeBaseUpdateLSMultiple()  local
1328       if (!STI->hasMinSize() || !BaseKill)  in MergeBaseUpdateLSMultiple()
1352     .addReg(Base, getKillRegState(BaseKill))  in MergeBaseUpdateLSMultiple()
1476   bool BaseKill = getLoadStoreBaseOp(*MI).isKill();  in MergeBaseUpdateLoadStore()  local
1533                    .addReg(Base, getKillRegState(isLd ? BaseKill : false))  in MergeBaseUpdateLoadStore()
1737                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,  in InsertLDR_STR()  argument
1744       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1753       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1796   bool BaseKill = BaseOp.isKill();  in FixInvalidRegPairOp()  local
1812         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1820         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1846                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1863                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()