Lines Matching full:arm
1 //===- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass -------------===//
14 #include "ARM.h"
74 #define DEBUG_TYPE "arm-ldst-opt"
94 AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
95 cl::init(false), cl::desc("Be more conservative in ARM load/store opt"));
97 #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
204 INITIALIZE_PASS(ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false,
211 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
226 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
227 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
228 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
229 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
233 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
234 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
259 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
263 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
264 case ARM_AM::da: return ARM::LDMDA; in getLoadStoreMultipleOpcode()
265 case ARM_AM::db: return ARM::LDMDB; in getLoadStoreMultipleOpcode()
266 case ARM_AM::ib: return ARM::LDMIB; in getLoadStoreMultipleOpcode()
268 case ARM::STRi12: in getLoadStoreMultipleOpcode()
272 case ARM_AM::ia: return ARM::STMIA; in getLoadStoreMultipleOpcode()
273 case ARM_AM::da: return ARM::STMDA; in getLoadStoreMultipleOpcode()
274 case ARM_AM::db: return ARM::STMDB; in getLoadStoreMultipleOpcode()
275 case ARM_AM::ib: return ARM::STMIB; in getLoadStoreMultipleOpcode()
277 case ARM::tLDRi: in getLoadStoreMultipleOpcode()
278 case ARM::tLDRspi: in getLoadStoreMultipleOpcode()
284 case ARM_AM::ia: return ARM::tLDMIA; in getLoadStoreMultipleOpcode()
286 case ARM::tSTRi: in getLoadStoreMultipleOpcode()
287 case ARM::tSTRspi: in getLoadStoreMultipleOpcode()
292 case ARM_AM::ia: return ARM::tSTMIA_UPD; in getLoadStoreMultipleOpcode()
294 case ARM::t2LDRi8: in getLoadStoreMultipleOpcode()
295 case ARM::t2LDRi12: in getLoadStoreMultipleOpcode()
299 case ARM_AM::ia: return ARM::t2LDMIA; in getLoadStoreMultipleOpcode()
300 case ARM_AM::db: return ARM::t2LDMDB; in getLoadStoreMultipleOpcode()
302 case ARM::t2STRi8: in getLoadStoreMultipleOpcode()
303 case ARM::t2STRi12: in getLoadStoreMultipleOpcode()
307 case ARM_AM::ia: return ARM::t2STMIA; in getLoadStoreMultipleOpcode()
308 case ARM_AM::db: return ARM::t2STMDB; in getLoadStoreMultipleOpcode()
310 case ARM::VLDRS: in getLoadStoreMultipleOpcode()
314 case ARM_AM::ia: return ARM::VLDMSIA; in getLoadStoreMultipleOpcode()
317 case ARM::VSTRS: in getLoadStoreMultipleOpcode()
321 case ARM_AM::ia: return ARM::VSTMSIA; in getLoadStoreMultipleOpcode()
324 case ARM::VLDRD: in getLoadStoreMultipleOpcode()
328 case ARM_AM::ia: return ARM::VLDMDIA; in getLoadStoreMultipleOpcode()
331 case ARM::VSTRD: in getLoadStoreMultipleOpcode()
335 case ARM_AM::ia: return ARM::VSTMDIA; in getLoadStoreMultipleOpcode()
344 case ARM::LDMIA_RET: in getLoadStoreMultipleSubMode()
345 case ARM::LDMIA: in getLoadStoreMultipleSubMode()
346 case ARM::LDMIA_UPD: in getLoadStoreMultipleSubMode()
347 case ARM::STMIA: in getLoadStoreMultipleSubMode()
348 case ARM::STMIA_UPD: in getLoadStoreMultipleSubMode()
349 case ARM::tLDMIA: in getLoadStoreMultipleSubMode()
350 case ARM::tLDMIA_UPD: in getLoadStoreMultipleSubMode()
351 case ARM::tSTMIA_UPD: in getLoadStoreMultipleSubMode()
352 case ARM::t2LDMIA_RET: in getLoadStoreMultipleSubMode()
353 case ARM::t2LDMIA: in getLoadStoreMultipleSubMode()
354 case ARM::t2LDMIA_UPD: in getLoadStoreMultipleSubMode()
355 case ARM::t2STMIA: in getLoadStoreMultipleSubMode()
356 case ARM::t2STMIA_UPD: in getLoadStoreMultipleSubMode()
357 case ARM::VLDMSIA: in getLoadStoreMultipleSubMode()
358 case ARM::VLDMSIA_UPD: in getLoadStoreMultipleSubMode()
359 case ARM::VSTMSIA: in getLoadStoreMultipleSubMode()
360 case ARM::VSTMSIA_UPD: in getLoadStoreMultipleSubMode()
361 case ARM::VLDMDIA: in getLoadStoreMultipleSubMode()
362 case ARM::VLDMDIA_UPD: in getLoadStoreMultipleSubMode()
363 case ARM::VSTMDIA: in getLoadStoreMultipleSubMode()
364 case ARM::VSTMDIA_UPD: in getLoadStoreMultipleSubMode()
367 case ARM::LDMDA: in getLoadStoreMultipleSubMode()
368 case ARM::LDMDA_UPD: in getLoadStoreMultipleSubMode()
369 case ARM::STMDA: in getLoadStoreMultipleSubMode()
370 case ARM::STMDA_UPD: in getLoadStoreMultipleSubMode()
373 case ARM::LDMDB: in getLoadStoreMultipleSubMode()
374 case ARM::LDMDB_UPD: in getLoadStoreMultipleSubMode()
375 case ARM::STMDB: in getLoadStoreMultipleSubMode()
376 case ARM::STMDB_UPD: in getLoadStoreMultipleSubMode()
377 case ARM::t2LDMDB: in getLoadStoreMultipleSubMode()
378 case ARM::t2LDMDB_UPD: in getLoadStoreMultipleSubMode()
379 case ARM::t2STMDB: in getLoadStoreMultipleSubMode()
380 case ARM::t2STMDB_UPD: in getLoadStoreMultipleSubMode()
381 case ARM::VLDMSDB_UPD: in getLoadStoreMultipleSubMode()
382 case ARM::VSTMSDB_UPD: in getLoadStoreMultipleSubMode()
383 case ARM::VLDMDDB_UPD: in getLoadStoreMultipleSubMode()
384 case ARM::VSTMDDB_UPD: in getLoadStoreMultipleSubMode()
387 case ARM::LDMIB: in getLoadStoreMultipleSubMode()
388 case ARM::LDMIB_UPD: in getLoadStoreMultipleSubMode()
389 case ARM::STMIB: in getLoadStoreMultipleSubMode()
390 case ARM::STMIB_UPD: in getLoadStoreMultipleSubMode()
396 return Opc == ARM::tLDRi || Opc == ARM::tLDRspi; in isT1i32Load()
400 return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8; in isT2i32Load()
404 return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ; in isi32Load()
408 return Opc == ARM::tSTRi || Opc == ARM::tSTRspi; in isT1i32Store()
412 return Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8; in isT2i32Store()
416 return Opc == ARM::STRi12 || isT1i32Store(Opc) || isT2i32Store(Opc); in isi32Store()
420 return isi32Load(Opc) || Opc == ARM::VLDRS || Opc == ARM::VLDRD; in isLoadSingle()
426 case ARM::tLDRi: in getImmScale()
427 case ARM::tSTRi: in getImmScale()
428 case ARM::tLDRspi: in getImmScale()
429 case ARM::tSTRspi: in getImmScale()
431 case ARM::tLDRHi: in getImmScale()
432 case ARM::tSTRHi: in getImmScale()
434 case ARM::tLDRBi: in getImmScale()
435 case ARM::tSTRBi: in getImmScale()
443 case ARM::LDRi12: in getLSMultipleTransferSize()
444 case ARM::STRi12: in getLSMultipleTransferSize()
445 case ARM::tLDRi: in getLSMultipleTransferSize()
446 case ARM::tSTRi: in getLSMultipleTransferSize()
447 case ARM::tLDRspi: in getLSMultipleTransferSize()
448 case ARM::tSTRspi: in getLSMultipleTransferSize()
449 case ARM::t2LDRi8: in getLSMultipleTransferSize()
450 case ARM::t2LDRi12: in getLSMultipleTransferSize()
451 case ARM::t2STRi8: in getLSMultipleTransferSize()
452 case ARM::t2STRi12: in getLSMultipleTransferSize()
453 case ARM::VLDRS: in getLSMultipleTransferSize()
454 case ARM::VSTRS: in getLSMultipleTransferSize()
456 case ARM::VLDRD: in getLSMultipleTransferSize()
457 case ARM::VSTRD: in getLSMultipleTransferSize()
459 case ARM::LDMIA: in getLSMultipleTransferSize()
460 case ARM::LDMDA: in getLSMultipleTransferSize()
461 case ARM::LDMDB: in getLSMultipleTransferSize()
462 case ARM::LDMIB: in getLSMultipleTransferSize()
463 case ARM::STMIA: in getLSMultipleTransferSize()
464 case ARM::STMDA: in getLSMultipleTransferSize()
465 case ARM::STMDB: in getLSMultipleTransferSize()
466 case ARM::STMIB: in getLSMultipleTransferSize()
467 case ARM::tLDMIA: in getLSMultipleTransferSize()
468 case ARM::tLDMIA_UPD: in getLSMultipleTransferSize()
469 case ARM::tSTMIA_UPD: in getLSMultipleTransferSize()
470 case ARM::t2LDMIA: in getLSMultipleTransferSize()
471 case ARM::t2LDMDB: in getLSMultipleTransferSize()
472 case ARM::t2STMIA: in getLSMultipleTransferSize()
473 case ARM::t2STMDB: in getLSMultipleTransferSize()
474 case ARM::VLDMSIA: in getLSMultipleTransferSize()
475 case ARM::VSTMSIA: in getLSMultipleTransferSize()
477 case ARM::VLDMDIA: in getLSMultipleTransferSize()
478 case ARM::VSTMDIA: in getLSMultipleTransferSize()
501 Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; in UpdateBaseRegUses()
503 Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi; in UpdateBaseRegUses()
522 } else if ((Opc == ARM::tSUBi8 || Opc == ARM::tADDi8) && in UpdateBaseRegUses()
529 Offset = (Opc == ARM::tSUBi8) ? in UpdateBaseRegUses()
554 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) in UpdateBaseRegUses()
576 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) in UpdateBaseRegUses()
640 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) == in CreateLoadStoreMulti()
649 assert(Base != ARM::SP && "Thumb1 does not allow SP in register list"); in CreateLoadStoreMulti()
650 if (Opcode == ARM::tLDRi) in CreateLoadStoreMulti()
652 else if (Opcode == ARM::tSTRi) in CreateLoadStoreMulti()
668 } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) { in CreateLoadStoreMulti()
699 NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass); in CreateLoadStoreMulti()
704 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm in CreateLoadStoreMulti()
705 : ARM::t2ADDri) in CreateLoadStoreMulti()
706 : (isThumb1 && Base == ARM::SP) in CreateLoadStoreMulti()
707 ? ARM::tADDrSPi in CreateLoadStoreMulti()
709 ? ARM::tADDi3 in CreateLoadStoreMulti()
710 : isThumb1 ? ARM::tADDi8 : ARM::ADDri; in CreateLoadStoreMulti()
714 // offsets. So the Base != ARM::SP might be unnecessary. in CreateLoadStoreMulti()
716 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm in CreateLoadStoreMulti()
717 : ARM::t2SUBri) in CreateLoadStoreMulti()
718 : (isThumb1 && Offset < 8 && Base != ARM::SP) in CreateLoadStoreMulti()
719 ? ARM::tSUBi3 in CreateLoadStoreMulti()
720 : isThumb1 ? ARM::tSUBi8 : ARM::SUBri; in CreateLoadStoreMulti()
739 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
746 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase) in CreateLoadStoreMulti()
749 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase) in CreateLoadStoreMulti()
757 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
803 if (Opcode == ARM::tLDMIA) { in CreateLoadStoreMulti()
806 Opcode = ARM::tLDMIA_UPD; in CreateLoadStoreMulti()
843 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8; in CreateLoadStoreDouble()
964 assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD); in MergeOpsUpdate()
998 if (getLoadStoreBaseOp(MI).getReg() == ARM::SP && in mayCombineMisaligned()
1026 // ARM errata 602117: LDRD with base in list may result in incorrect base in FormCandidates()
1040 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
1053 case ARM::VLDRD: in FormCandidates()
1054 case ARM::VSTRD: in FormCandidates()
1066 if (Reg == ARM::SP || Reg == ARM::PC) in FormCandidates()
1125 case ARM::LDMIA: in getUpdatingLSMultipleOpcode()
1126 case ARM::LDMDA: in getUpdatingLSMultipleOpcode()
1127 case ARM::LDMDB: in getUpdatingLSMultipleOpcode()
1128 case ARM::LDMIB: in getUpdatingLSMultipleOpcode()
1131 case ARM_AM::ia: return ARM::LDMIA_UPD; in getUpdatingLSMultipleOpcode()
1132 case ARM_AM::ib: return ARM::LDMIB_UPD; in getUpdatingLSMultipleOpcode()
1133 case ARM_AM::da: return ARM::LDMDA_UPD; in getUpdatingLSMultipleOpcode()
1134 case ARM_AM::db: return ARM::LDMDB_UPD; in getUpdatingLSMultipleOpcode()
1136 case ARM::STMIA: in getUpdatingLSMultipleOpcode()
1137 case ARM::STMDA: in getUpdatingLSMultipleOpcode()
1138 case ARM::STMDB: in getUpdatingLSMultipleOpcode()
1139 case ARM::STMIB: in getUpdatingLSMultipleOpcode()
1142 case ARM_AM::ia: return ARM::STMIA_UPD; in getUpdatingLSMultipleOpcode()
1143 case ARM_AM::ib: return ARM::STMIB_UPD; in getUpdatingLSMultipleOpcode()
1144 case ARM_AM::da: return ARM::STMDA_UPD; in getUpdatingLSMultipleOpcode()
1145 case ARM_AM::db: return ARM::STMDB_UPD; in getUpdatingLSMultipleOpcode()
1147 case ARM::t2LDMIA: in getUpdatingLSMultipleOpcode()
1148 case ARM::t2LDMDB: in getUpdatingLSMultipleOpcode()
1151 case ARM_AM::ia: return ARM::t2LDMIA_UPD; in getUpdatingLSMultipleOpcode()
1152 case ARM_AM::db: return ARM::t2LDMDB_UPD; in getUpdatingLSMultipleOpcode()
1154 case ARM::t2STMIA: in getUpdatingLSMultipleOpcode()
1155 case ARM::t2STMDB: in getUpdatingLSMultipleOpcode()
1158 case ARM_AM::ia: return ARM::t2STMIA_UPD; in getUpdatingLSMultipleOpcode()
1159 case ARM_AM::db: return ARM::t2STMDB_UPD; in getUpdatingLSMultipleOpcode()
1161 case ARM::VLDMSIA: in getUpdatingLSMultipleOpcode()
1164 case ARM_AM::ia: return ARM::VLDMSIA_UPD; in getUpdatingLSMultipleOpcode()
1165 case ARM_AM::db: return ARM::VLDMSDB_UPD; in getUpdatingLSMultipleOpcode()
1167 case ARM::VLDMDIA: in getUpdatingLSMultipleOpcode()
1170 case ARM_AM::ia: return ARM::VLDMDIA_UPD; in getUpdatingLSMultipleOpcode()
1171 case ARM_AM::db: return ARM::VLDMDDB_UPD; in getUpdatingLSMultipleOpcode()
1173 case ARM::VSTMSIA: in getUpdatingLSMultipleOpcode()
1176 case ARM_AM::ia: return ARM::VSTMSIA_UPD; in getUpdatingLSMultipleOpcode()
1177 case ARM_AM::db: return ARM::VSTMSDB_UPD; in getUpdatingLSMultipleOpcode()
1179 case ARM::VSTMDIA: in getUpdatingLSMultipleOpcode()
1182 case ARM_AM::ia: return ARM::VSTMDIA_UPD; in getUpdatingLSMultipleOpcode()
1183 case ARM_AM::db: return ARM::VSTMDDB_UPD; in getUpdatingLSMultipleOpcode()
1196 case ARM::tADDi8: Scale = 4; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1197 case ARM::tSUBi8: Scale = -4; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1198 case ARM::t2SUBri: in isIncrementOrDecrement()
1199 case ARM::t2SUBspImm: in isIncrementOrDecrement()
1200 case ARM::SUBri: Scale = -1; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1201 case ARM::t2ADDri: in isIncrementOrDecrement()
1202 case ARM::t2ADDspImm: in isIncrementOrDecrement()
1203 case ARM::ADDri: Scale = 1; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1204 case ARM::tADDspi: Scale = 4; CheckCPSRDef = false; break; in isIncrementOrDecrement()
1205 case ARM::tSUBspi: Scale = -4; CheckCPSRDef = false; break; in isIncrementOrDecrement()
1268 if (Reg == ARM::SP || NextMBBI->readsRegister(Reg, TRI) || in findIncDecAfter()
1333 if (MO.getReg() >= ARM::R8) { in MergeBaseUpdateLSMultiple()
1370 case ARM::LDRi12: in getPreIndexedLoadStoreOpcode()
1371 return ARM::LDR_PRE_IMM; in getPreIndexedLoadStoreOpcode()
1372 case ARM::STRi12: in getPreIndexedLoadStoreOpcode()
1373 return ARM::STR_PRE_IMM; in getPreIndexedLoadStoreOpcode()
1374 case ARM::VLDRS: in getPreIndexedLoadStoreOpcode()
1375 return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; in getPreIndexedLoadStoreOpcode()
1376 case ARM::VLDRD: in getPreIndexedLoadStoreOpcode()
1377 return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD; in getPreIndexedLoadStoreOpcode()
1378 case ARM::VSTRS: in getPreIndexedLoadStoreOpcode()
1379 return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD; in getPreIndexedLoadStoreOpcode()
1380 case ARM::VSTRD: in getPreIndexedLoadStoreOpcode()
1381 return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD; in getPreIndexedLoadStoreOpcode()
1382 case ARM::t2LDRi8: in getPreIndexedLoadStoreOpcode()
1383 case ARM::t2LDRi12: in getPreIndexedLoadStoreOpcode()
1384 return ARM::t2LDR_PRE; in getPreIndexedLoadStoreOpcode()
1385 case ARM::t2STRi8: in getPreIndexedLoadStoreOpcode()
1386 case ARM::t2STRi12: in getPreIndexedLoadStoreOpcode()
1387 return ARM::t2STR_PRE; in getPreIndexedLoadStoreOpcode()
1395 case ARM::LDRi12: in getPostIndexedLoadStoreOpcode()
1396 return ARM::LDR_POST_IMM; in getPostIndexedLoadStoreOpcode()
1397 case ARM::STRi12: in getPostIndexedLoadStoreOpcode()
1398 return ARM::STR_POST_IMM; in getPostIndexedLoadStoreOpcode()
1399 case ARM::VLDRS: in getPostIndexedLoadStoreOpcode()
1400 return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; in getPostIndexedLoadStoreOpcode()
1401 case ARM::VLDRD: in getPostIndexedLoadStoreOpcode()
1402 return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD; in getPostIndexedLoadStoreOpcode()
1403 case ARM::VSTRS: in getPostIndexedLoadStoreOpcode()
1404 return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD; in getPostIndexedLoadStoreOpcode()
1405 case ARM::VSTRD: in getPostIndexedLoadStoreOpcode()
1406 return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD; in getPostIndexedLoadStoreOpcode()
1407 case ARM::t2LDRi8: in getPostIndexedLoadStoreOpcode()
1408 case ARM::t2LDRi12: in getPostIndexedLoadStoreOpcode()
1409 return ARM::t2LDR_POST; in getPostIndexedLoadStoreOpcode()
1410 case ARM::t2LDRBi8: in getPostIndexedLoadStoreOpcode()
1411 case ARM::t2LDRBi12: in getPostIndexedLoadStoreOpcode()
1412 return ARM::t2LDRB_POST; in getPostIndexedLoadStoreOpcode()
1413 case ARM::t2LDRSBi8: in getPostIndexedLoadStoreOpcode()
1414 case ARM::t2LDRSBi12: in getPostIndexedLoadStoreOpcode()
1415 return ARM::t2LDRSB_POST; in getPostIndexedLoadStoreOpcode()
1416 case ARM::t2LDRHi8: in getPostIndexedLoadStoreOpcode()
1417 case ARM::t2LDRHi12: in getPostIndexedLoadStoreOpcode()
1418 return ARM::t2LDRH_POST; in getPostIndexedLoadStoreOpcode()
1419 case ARM::t2LDRSHi8: in getPostIndexedLoadStoreOpcode()
1420 case ARM::t2LDRSHi12: in getPostIndexedLoadStoreOpcode()
1421 return ARM::t2LDRSH_POST; in getPostIndexedLoadStoreOpcode()
1422 case ARM::t2STRi8: in getPostIndexedLoadStoreOpcode()
1423 case ARM::t2STRi12: in getPostIndexedLoadStoreOpcode()
1424 return ARM::t2STR_POST; in getPostIndexedLoadStoreOpcode()
1425 case ARM::t2STRBi8: in getPostIndexedLoadStoreOpcode()
1426 case ARM::t2STRBi12: in getPostIndexedLoadStoreOpcode()
1427 return ARM::t2STRB_POST; in getPostIndexedLoadStoreOpcode()
1428 case ARM::t2STRHi8: in getPostIndexedLoadStoreOpcode()
1429 case ARM::t2STRHi12: in getPostIndexedLoadStoreOpcode()
1430 return ARM::t2STRH_POST; in getPostIndexedLoadStoreOpcode()
1432 case ARM::MVE_VLDRBS16: in getPostIndexedLoadStoreOpcode()
1433 return ARM::MVE_VLDRBS16_post; in getPostIndexedLoadStoreOpcode()
1434 case ARM::MVE_VLDRBS32: in getPostIndexedLoadStoreOpcode()
1435 return ARM::MVE_VLDRBS32_post; in getPostIndexedLoadStoreOpcode()
1436 case ARM::MVE_VLDRBU16: in getPostIndexedLoadStoreOpcode()
1437 return ARM::MVE_VLDRBU16_post; in getPostIndexedLoadStoreOpcode()
1438 case ARM::MVE_VLDRBU32: in getPostIndexedLoadStoreOpcode()
1439 return ARM::MVE_VLDRBU32_post; in getPostIndexedLoadStoreOpcode()
1440 case ARM::MVE_VLDRHS32: in getPostIndexedLoadStoreOpcode()
1441 return ARM::MVE_VLDRHS32_post; in getPostIndexedLoadStoreOpcode()
1442 case ARM::MVE_VLDRHU32: in getPostIndexedLoadStoreOpcode()
1443 return ARM::MVE_VLDRHU32_post; in getPostIndexedLoadStoreOpcode()
1444 case ARM::MVE_VLDRBU8: in getPostIndexedLoadStoreOpcode()
1445 return ARM::MVE_VLDRBU8_post; in getPostIndexedLoadStoreOpcode()
1446 case ARM::MVE_VLDRHU16: in getPostIndexedLoadStoreOpcode()
1447 return ARM::MVE_VLDRHU16_post; in getPostIndexedLoadStoreOpcode()
1448 case ARM::MVE_VLDRWU32: in getPostIndexedLoadStoreOpcode()
1449 return ARM::MVE_VLDRWU32_post; in getPostIndexedLoadStoreOpcode()
1450 case ARM::MVE_VSTRB16: in getPostIndexedLoadStoreOpcode()
1451 return ARM::MVE_VSTRB16_post; in getPostIndexedLoadStoreOpcode()
1452 case ARM::MVE_VSTRB32: in getPostIndexedLoadStoreOpcode()
1453 return ARM::MVE_VSTRB32_post; in getPostIndexedLoadStoreOpcode()
1454 case ARM::MVE_VSTRH32: in getPostIndexedLoadStoreOpcode()
1455 return ARM::MVE_VSTRH32_post; in getPostIndexedLoadStoreOpcode()
1456 case ARM::MVE_VSTRBU8: in getPostIndexedLoadStoreOpcode()
1457 return ARM::MVE_VSTRBU8_post; in getPostIndexedLoadStoreOpcode()
1458 case ARM::MVE_VSTRHU16: in getPostIndexedLoadStoreOpcode()
1459 return ARM::MVE_VSTRHU16_post; in getPostIndexedLoadStoreOpcode()
1460 case ARM::MVE_VSTRWU32: in getPostIndexedLoadStoreOpcode()
1461 return ARM::MVE_VSTRWU32_post; in getPostIndexedLoadStoreOpcode()
1479 bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS || in MergeBaseUpdateLoadStore()
1480 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS); in MergeBaseUpdateLoadStore()
1481 bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12); in MergeBaseUpdateLoadStore()
1544 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1585 if (isAM2 && NewOpc == ARM::STR_POST_IMM) { in MergeBaseUpdateLoadStore()
1616 assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) && in MergeBaseUpdateLSDouble()
1640 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1645 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1654 if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) { in MergeBaseUpdateLSDouble()
1657 assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST); in MergeBaseUpdateLSDouble()
1681 case ARM::VLDRS: in isMemoryOp()
1682 case ARM::VSTRS: in isMemoryOp()
1683 case ARM::VLDRD: in isMemoryOp()
1684 case ARM::VSTRD: in isMemoryOp()
1685 case ARM::LDRi12: in isMemoryOp()
1686 case ARM::STRi12: in isMemoryOp()
1687 case ARM::tLDRi: in isMemoryOp()
1688 case ARM::tSTRi: in isMemoryOp()
1689 case ARM::tLDRspi: in isMemoryOp()
1690 case ARM::tSTRspi: in isMemoryOp()
1691 case ARM::t2LDRi8: in isMemoryOp()
1692 case ARM::t2LDRi12: in isMemoryOp()
1693 case ARM::t2STRi8: in isMemoryOp()
1694 case ARM::t2STRi12: in isMemoryOp()
1767 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1777 // ARM errata 602117: LDRD with base in list may result in incorrect base in FixInvalidRegPairOp()
1780 (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3(); in FixInvalidRegPairOp()
1781 // ARM LDRD/STRD needs consecutive registers. in FixInvalidRegPairOp()
1782 bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) && in FixInvalidRegPairOp()
1788 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8; in FixInvalidRegPairOp()
1789 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp()
1798 assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) && in FixInvalidRegPairOp()
1808 ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA) in FixInvalidRegPairOp()
1809 : (isT2 ? ARM::t2STMIA : ARM::STMIA); in FixInvalidRegPairOp()
1832 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1833 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1837 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1838 : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1966 } else if (MBBI->getOpcode() == ARM::t2LDRDi8 || in LoadStoreMultipleOpti()
1967 MBBI->getOpcode() == ARM::t2STRDi8) { in LoadStoreMultipleOpti()
2002 if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8) in LoadStoreMultipleOpti()
2044 (MBBI->getOpcode() == ARM::BX_RET || in MergeReturnIntoLDM()
2045 MBBI->getOpcode() == ARM::tBX_RET || in MergeReturnIntoLDM()
2046 MBBI->getOpcode() == ARM::MOVPCLR)) { in MergeReturnIntoLDM()
2053 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD || in MergeReturnIntoLDM()
2054 Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD || in MergeReturnIntoLDM()
2055 Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { in MergeReturnIntoLDM()
2057 if (MO.getReg() != ARM::LR) in MergeReturnIntoLDM()
2059 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM()
2060 assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) || in MergeReturnIntoLDM()
2061 Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!"); in MergeReturnIntoLDM()
2063 MO.setReg(ARM::PC); in MergeReturnIntoLDM()
2075 MBBI->getOpcode() != ARM::tBX_RET) in CombineMovBx()
2080 if (Prev->getOpcode() != ARM::tMOVr || in CombineMovBx()
2081 !Prev->definesRegister(ARM::LR, /*TRI=*/nullptr)) in CombineMovBx()
2087 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX)) in CombineMovBx()
2136 "ARM pre- register allocation load / store optimization pass"
2187 INITIALIZE_PASS_BEGIN(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
2190 INITIALIZE_PASS_END(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
2195 static cl::opt<unsigned> InstReorderLimit("arm-prera-ldst-opt-reorder-limit",
2266 if (Opcode == ARM::LDRi12) { in CanFormLdStDWord()
2267 NewOpc = ARM::LDRD; in CanFormLdStDWord()
2268 } else if (Opcode == ARM::STRi12) { in CanFormLdStDWord()
2269 NewOpc = ARM::STRD; in CanFormLdStDWord()
2270 } else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) { in CanFormLdStDWord()
2271 NewOpc = ARM::t2LDRDi8; in CanFormLdStDWord()
2274 } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) { in CanFormLdStDWord()
2275 NewOpc = ARM::t2STRDi8; in CanFormLdStDWord()
2883 case ARM::MVE_VLDRBS16: in getBaseOperandIndex()
2884 case ARM::MVE_VLDRBS32: in getBaseOperandIndex()
2885 case ARM::MVE_VLDRBU16: in getBaseOperandIndex()
2886 case ARM::MVE_VLDRBU32: in getBaseOperandIndex()
2887 case ARM::MVE_VLDRHS32: in getBaseOperandIndex()
2888 case ARM::MVE_VLDRHU32: in getBaseOperandIndex()
2889 case ARM::MVE_VLDRBU8: in getBaseOperandIndex()
2890 case ARM::MVE_VLDRHU16: in getBaseOperandIndex()
2891 case ARM::MVE_VLDRWU32: in getBaseOperandIndex()
2892 case ARM::MVE_VSTRB16: in getBaseOperandIndex()
2893 case ARM::MVE_VSTRB32: in getBaseOperandIndex()
2894 case ARM::MVE_VSTRH32: in getBaseOperandIndex()
2895 case ARM::MVE_VSTRBU8: in getBaseOperandIndex()
2896 case ARM::MVE_VSTRHU16: in getBaseOperandIndex()
2897 case ARM::MVE_VSTRWU32: in getBaseOperandIndex()
2898 case ARM::t2LDRHi8: in getBaseOperandIndex()
2899 case ARM::t2LDRHi12: in getBaseOperandIndex()
2900 case ARM::t2LDRSHi8: in getBaseOperandIndex()
2901 case ARM::t2LDRSHi12: in getBaseOperandIndex()
2902 case ARM::t2LDRBi8: in getBaseOperandIndex()
2903 case ARM::t2LDRBi12: in getBaseOperandIndex()
2904 case ARM::t2LDRSBi8: in getBaseOperandIndex()
2905 case ARM::t2LDRSBi12: in getBaseOperandIndex()
2906 case ARM::t2STRBi8: in getBaseOperandIndex()
2907 case ARM::t2STRBi12: in getBaseOperandIndex()
2908 case ARM::t2STRHi8: in getBaseOperandIndex()
2909 case ARM::t2STRHi12: in getBaseOperandIndex()
2911 case ARM::MVE_VLDRBS16_post: in getBaseOperandIndex()
2912 case ARM::MVE_VLDRBS32_post: in getBaseOperandIndex()
2913 case ARM::MVE_VLDRBU16_post: in getBaseOperandIndex()
2914 case ARM::MVE_VLDRBU32_post: in getBaseOperandIndex()
2915 case ARM::MVE_VLDRHS32_post: in getBaseOperandIndex()
2916 case ARM::MVE_VLDRHU32_post: in getBaseOperandIndex()
2917 case ARM::MVE_VLDRBU8_post: in getBaseOperandIndex()
2918 case ARM::MVE_VLDRHU16_post: in getBaseOperandIndex()
2919 case ARM::MVE_VLDRWU32_post: in getBaseOperandIndex()
2920 case ARM::MVE_VSTRB16_post: in getBaseOperandIndex()
2921 case ARM::MVE_VSTRB32_post: in getBaseOperandIndex()
2922 case ARM::MVE_VSTRH32_post: in getBaseOperandIndex()
2923 case ARM::MVE_VSTRBU8_post: in getBaseOperandIndex()
2924 case ARM::MVE_VSTRHU16_post: in getBaseOperandIndex()
2925 case ARM::MVE_VSTRWU32_post: in getBaseOperandIndex()
2926 case ARM::MVE_VLDRBS16_pre: in getBaseOperandIndex()
2927 case ARM::MVE_VLDRBS32_pre: in getBaseOperandIndex()
2928 case ARM::MVE_VLDRBU16_pre: in getBaseOperandIndex()
2929 case ARM::MVE_VLDRBU32_pre: in getBaseOperandIndex()
2930 case ARM::MVE_VLDRHS32_pre: in getBaseOperandIndex()
2931 case ARM::MVE_VLDRHU32_pre: in getBaseOperandIndex()
2932 case ARM::MVE_VLDRBU8_pre: in getBaseOperandIndex()
2933 case ARM::MVE_VLDRHU16_pre: in getBaseOperandIndex()
2934 case ARM::MVE_VLDRWU32_pre: in getBaseOperandIndex()
2935 case ARM::MVE_VSTRB16_pre: in getBaseOperandIndex()
2936 case ARM::MVE_VSTRB32_pre: in getBaseOperandIndex()
2937 case ARM::MVE_VSTRH32_pre: in getBaseOperandIndex()
2938 case ARM::MVE_VSTRBU8_pre: in getBaseOperandIndex()
2939 case ARM::MVE_VSTRHU16_pre: in getBaseOperandIndex()
2940 case ARM::MVE_VSTRWU32_pre: in getBaseOperandIndex()
2948 case ARM::MVE_VLDRBS16_post: in isPostIndex()
2949 case ARM::MVE_VLDRBS32_post: in isPostIndex()
2950 case ARM::MVE_VLDRBU16_post: in isPostIndex()
2951 case ARM::MVE_VLDRBU32_post: in isPostIndex()
2952 case ARM::MVE_VLDRHS32_post: in isPostIndex()
2953 case ARM::MVE_VLDRHU32_post: in isPostIndex()
2954 case ARM::MVE_VLDRBU8_post: in isPostIndex()
2955 case ARM::MVE_VLDRHU16_post: in isPostIndex()
2956 case ARM::MVE_VLDRWU32_post: in isPostIndex()
2957 case ARM::MVE_VSTRB16_post: in isPostIndex()
2958 case ARM::MVE_VSTRB32_post: in isPostIndex()
2959 case ARM::MVE_VSTRH32_post: in isPostIndex()
2960 case ARM::MVE_VSTRBU8_post: in isPostIndex()
2961 case ARM::MVE_VSTRHU16_post: in isPostIndex()
2962 case ARM::MVE_VSTRWU32_post: in isPostIndex()
2970 case ARM::MVE_VLDRBS16_pre: in isPreIndex()
2971 case ARM::MVE_VLDRBS32_pre: in isPreIndex()
2972 case ARM::MVE_VLDRBU16_pre: in isPreIndex()
2973 case ARM::MVE_VLDRBU32_pre: in isPreIndex()
2974 case ARM::MVE_VLDRHS32_pre: in isPreIndex()
2975 case ARM::MVE_VLDRHU32_pre: in isPreIndex()
2976 case ARM::MVE_VLDRBU8_pre: in isPreIndex()
2977 case ARM::MVE_VLDRHU16_pre: in isPreIndex()
2978 case ARM::MVE_VLDRWU32_pre: in isPreIndex()
2979 case ARM::MVE_VSTRB16_pre: in isPreIndex()
2980 case ARM::MVE_VSTRB32_pre: in isPreIndex()
2981 case ARM::MVE_VSTRH32_pre: in isPreIndex()
2982 case ARM::MVE_VSTRBU8_pre: in isPreIndex()
2983 case ARM::MVE_VSTRHU16_pre: in isPreIndex()
2984 case ARM::MVE_VSTRWU32_pre: in isPreIndex()
3034 case ARM::t2LDRHi12: in AdjustBaseAndOffset()
3035 ConvOpcode = ARM::t2LDRHi8; in AdjustBaseAndOffset()
3037 case ARM::t2LDRSHi12: in AdjustBaseAndOffset()
3038 ConvOpcode = ARM::t2LDRSHi8; in AdjustBaseAndOffset()
3040 case ARM::t2LDRBi12: in AdjustBaseAndOffset()
3041 ConvOpcode = ARM::t2LDRBi8; in AdjustBaseAndOffset()
3043 case ARM::t2LDRSBi12: in AdjustBaseAndOffset()
3044 ConvOpcode = ARM::t2LDRSBi8; in AdjustBaseAndOffset()
3046 case ARM::t2STRHi12: in AdjustBaseAndOffset()
3047 ConvOpcode = ARM::t2STRHi8; in AdjustBaseAndOffset()
3049 case ARM::t2STRBi12: in AdjustBaseAndOffset()
3050 ConvOpcode = ARM::t2STRBi8; in AdjustBaseAndOffset()
3181 if (Increment->definesRegister(ARM::CPSR, /*TRI=*/nullptr) || in DistributeIncrements()