Lines Matching full:sd
159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
160 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>,
169 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),
170 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",
171 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>,
194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
195 IIC_fpStore32, "vstr", "\t$Sd, $addr",
196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>,
204 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),
205 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",
206 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>,
209 def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode5fp16:$addr),
210 (VSTRH (bf16 HPR:$Sd), addrmode5fp16:$addr)> {
213 def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode3:$addr),
214 (STRH (COPY_TO_REGCLASS $Sd, GPR), addrmode3:$addr)> {
217 def : Pat<(alignedstore16 (bf16 HPR:$Sd), t2addrmode_imm12:$addr),
218 (t2STRHi12 (COPY_TO_REGCLASS $Sd, GPR), t2addrmode_imm12:$addr)> {
432 let TwoOperandAliasConstraint = "$Sn = $Sd" in
434 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
435 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
436 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>,
443 let TwoOperandAliasConstraint = "$Sn = $Sd" in
445 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
446 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
447 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
457 let TwoOperandAliasConstraint = "$Sn = $Sd" in
459 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
460 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
461 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>,
468 let TwoOperandAliasConstraint = "$Sn = $Sd" in
470 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
471 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
472 [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
482 let TwoOperandAliasConstraint = "$Sn = $Sd" in
484 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
485 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
486 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
489 let TwoOperandAliasConstraint = "$Sn = $Sd" in
491 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
492 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
493 [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
503 let TwoOperandAliasConstraint = "$Sn = $Sd" in
505 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
506 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
507 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>,
514 let TwoOperandAliasConstraint = "$Sn = $Sd" in
516 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
517 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
518 [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
528 let TwoOperandAliasConstraint = "$Sn = $Sd" in
530 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
531 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
532 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>,
539 let TwoOperandAliasConstraint = "$Sn = $Sd" in
541 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
542 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
543 [(set (f16 HPR:$Sd), (fneg (fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>,
550 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
551 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
552 [(set (f16 HPR:$Sd), (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC))]>,
556 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
557 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
558 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
575 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
579 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
580 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
581 [(set (f16 HPR:$Sd), (SD (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
585 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
586 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
587 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
593 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
616 (outs), (ins SPR:$Sd, SPR:$Sm),
617 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", "",
618 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> {
625 (outs), (ins HPR:$Sd, HPR:$Sm),
626 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
627 [(arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
635 (outs), (ins SPR:$Sd, SPR:$Sm),
636 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", "",
637 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
644 (outs), (ins HPR:$Sd, HPR:$Sm),
645 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
646 [(arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
659 (outs SPR:$Sd), (ins SPR:$Sm),
660 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
661 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
668 (outs HPR:$Sd), (ins HPR:$Sm),
669 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",
670 [(set (f16 HPR:$Sd), (fabs (f16 HPR:$Sm)))]>;
682 (outs), (ins SPR:$Sd),
683 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", "",
684 [(arm_cmpfpe0 SPR:$Sd)]> {
694 (outs), (ins HPR:$Sd),
695 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
696 [(arm_cmpfpe0 (f16 HPR:$Sd))]> {
710 (outs), (ins SPR:$Sd),
711 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", "",
712 [(arm_cmpfp0 SPR:$Sd)]> {
722 (outs), (ins HPR:$Sd),
723 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
724 [(arm_cmpfp0 (f16 HPR:$Sd))]> {
750 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
751 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", "",
752 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
755 bits<5> Sd;
761 let Inst{15-12} = Sd{4-1};
762 let Inst{22} = Sd{0};
776 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
777 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", "",
788 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
789 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda",
810 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
811 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", "",
824 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
825 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda",
865 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
866 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",
870 bits<5> Sd;
876 let Inst{15-12} = Sd{4-1};
877 let Inst{22} = Sd{0};
904 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
905 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",
908 bits<5> Sd;
912 let Inst{15-12} = Sd{4-1};
913 let Inst{22} = Sd{0};
924 (outs SPR:$Sd), (ins HPR:$Sm),
925 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
932 (outs SPR:$Sd), (ins HPR:$Sm),
933 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),
940 (outs SPR:$Sd), (ins SPR:$Sm),
941 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
948 (outs SPR:$Sd), (ins SPR:$Sm),
949 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
955 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
956 (outs SPR:$Sd), (ins DPR:$Dm),
957 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
971 (outs SPR:$Sd), (ins DPR:$Dm),
972 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
1010 (!cast<Instruction>(NAME#"SD") DPR:$a),
1030 (outs SPR:$Sd), (ins SPR:$Sm),
1031 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
1032 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
1039 (outs HPR:$Sd), (ins HPR:$Sm),
1040 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
1041 [(set (f16 HPR:$Sd), (fneg (f16 HPR:$Sm)))]>;
1045 (outs HPR:$Sd), (ins HPR:$Sm),
1046 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
1047 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
1054 (outs SPR:$Sd), (ins SPR:$Sm),
1055 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", "",
1056 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1070 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),
1071 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1073 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
1074 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1090 (outs HPR:$Sd), (ins HPR:$Sm),
1091 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
1092 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
1097 (outs SPR:$Sd), (ins SPR:$Sm),
1098 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
1099 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1112 def : InstAlias<!strconcat("vrint", opc, ".f16.f16\t$Sd, $Sm"),
1113 (!cast<Instruction>(NAME#"H") HPR:$Sd, HPR:$Sm), 0>,
1115 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
1116 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
1135 (outs SPR:$Sd), (ins SPR:$Sm),
1136 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", "",
1137 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>,
1141 (outs HPR:$Sd), (ins HPR:$Sm),
1142 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
1143 [(set (f16 HPR:$Sd), (fsqrt (f16 HPR:$Sm)))]>;
1153 (outs SPR:$Sd), (ins SPR:$Sm),
1154 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", "", []>,
1160 (outs SPR:$Sd), (ins SPR:$Sm),
1161 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
1165 (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
1166 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
1168 let Constraints = "$Sd = $Sda";
1442 bits<5> Sd;
1448 let Inst{15-12} = Sd{4-1};
1449 let Inst{22} = Sd{0};
1461 bits<5> Sd;
1467 let Inst{15-12} = Sd{4-1};
1468 let Inst{22} = Sd{0};
1491 (outs SPR:$Sd),(ins SPR:$Sm),
1492 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1509 (outs HPR:$Sd), (ins SPR:$Sm),
1510 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",
1537 (outs SPR:$Sd), (ins SPR:$Sm),
1538 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1555 (outs HPR:$Sd), (ins SPR:$Sm),
1556 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",
1575 bits<5> Sd;
1581 let Inst{15-12} = Sd{4-1};
1582 let Inst{22} = Sd{0};
1595 bits<5> Sd;
1601 let Inst{15-12} = Sd{4-1};
1602 let Inst{22} = Sd{0};
1614 bits<5> Sd;
1620 let Inst{15-12} = Sd{4-1};
1621 let Inst{22} = Sd{0};
1629 (outs SPR:$Sd), (ins DPR:$Dm),
1630 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1649 (outs SPR:$Sd), (ins SPR:$Sm),
1650 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1673 (outs SPR:$Sd), (ins HPR:$Sm),
1674 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
1687 (outs SPR:$Sd), (ins DPR:$Dm),
1688 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1707 (outs SPR:$Sd), (ins SPR:$Sm),
1708 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1731 (outs SPR:$Sd), (ins HPR:$Sm),
1732 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
1747 (outs SPR:$Sd), (ins DPR:$Dm),
1748 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1749 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
1755 (outs SPR:$Sd), (ins SPR:$Sm),
1756 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1757 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>,
1763 (outs SPR:$Sd), (ins SPR:$Sm),
1764 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1772 (outs SPR:$Sd), (ins DPR:$Dm),
1773 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1774 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,
1780 (outs SPR:$Sd), (ins SPR:$Sm),
1781 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1782 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>,
1788 (outs SPR:$Sd), (ins SPR:$Sm),
1789 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
1799 (outs SPR:$Sd), (ins DPR:$Dm),
1800 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm",
2018 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm),
2020 opc, ".bf16.f32\t$Sd, $Sm", "", []>,
2021 RegConstraint<"$dst = $Sd">,
2024 bits<5> Sd;
2030 let Inst{15-12} = Sd{4-1};
2031 let Inst{22} = Sd{0};
2061 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2062 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
2063 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2065 RegConstraint<"$Sdin = $Sd">,
2074 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2075 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",
2076 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)),
2078 RegConstraint<"$Sdin = $Sd">,
2102 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2103 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
2104 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2106 RegConstraint<"$Sdin = $Sd">,
2115 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2116 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",
2117 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2119 RegConstraint<"$Sdin = $Sd">,
2142 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2143 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
2144 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2146 RegConstraint<"$Sdin = $Sd">,
2155 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2156 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",
2157 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2159 RegConstraint<"$Sdin = $Sd">,
2194 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2195 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
2196 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2197 RegConstraint<"$Sdin = $Sd">,
2206 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2207 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",
2208 … [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>,
2209 RegConstraint<"$Sdin = $Sd">,
2235 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2236 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
2237 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2239 RegConstraint<"$Sdin = $Sd">,
2247 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2248 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",
2249 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)),
2251 RegConstraint<"$Sdin = $Sd">,
2287 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2288 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
2289 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2291 RegConstraint<"$Sdin = $Sd">,
2299 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2300 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
2301 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2303 RegConstraint<"$Sdin = $Sd">,
2339 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2340 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
2341 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2343 RegConstraint<"$Sdin = $Sd">,
2351 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2352 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",
2353 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2355 RegConstraint<"$Sdin = $Sd">,
2398 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2399 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
2400 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2401 RegConstraint<"$Sdin = $Sd">,
2409 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2410 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
2411 … [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>,
2412 RegConstraint<"$Sdin = $Sd">,
2457 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2459 [(set (f32 SPR:$Sd),
2461 RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>;
2463 def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p),
2465 [(set (f16 HPR:$Sd),
2467 RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>;
2651 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2653 "vmov", ".f32\t$Sd, $imm", "",
2654 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2655 bits<5> Sd;
2659 let Inst{22} = Sd{0};
2662 let Inst{15-12} = Sd{4-1};
2669 def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm),
2671 "vmov", ".f16\t$Sd, $imm", "",
2672 [(set (f16 HPR:$Sd), vfp_f16imm:$imm)]>,
2674 bits<5> Sd;
2678 let Inst{22} = Sd{0};
2681 let Inst{15-12} = Sd{4-1};
2755 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
2756 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2759 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
2760 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2765 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2769 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
2770 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2771 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
2772 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2799 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
2800 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2810 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
2811 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;