Lines Matching full:dm
427 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
428 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
429 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>,
452 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
453 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
454 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>,
477 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
478 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
479 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>,
498 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
499 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
500 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>,
523 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
524 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
525 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>,
562 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
563 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
564 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
591 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
592 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
593 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
611 (outs), (ins DPR:$Dd, DPR:$Dm),
612 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", "",
613 [(arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm))]>;
630 (outs), (ins DPR:$Dd, DPR:$Dm),
631 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", "",
632 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
654 (outs DPR:$Dd), (ins DPR:$Dm),
655 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", "",
656 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
750 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
751 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", "",
752 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
756 bits<5> Dm;
759 let Inst{3-0} = Dm{3-0};
760 let Inst{5} = Dm{4};
865 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
866 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",
871 bits<5> Dm;
874 let Inst{3-0} = Dm{3-0};
875 let Inst{5} = Dm{4};
882 def : FullFP16Pat<(f16 (fpround DPR:$Dm)),
883 (COPY_TO_REGCLASS (VCVTBDH (IMPLICIT_DEF), DPR:$Dm), HPR)>,
904 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
905 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",
909 bits<5> Dm;
914 let Inst{3-0} = Dm{3-0};
915 let Inst{5} = Dm{4};
956 (outs SPR:$Sd), (ins DPR:$Dm),
957 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
960 bits<5> Dm;
965 let Inst{3-0} = Dm{3-0};
966 let Inst{5} = Dm{4};
971 (outs SPR:$Sd), (ins DPR:$Dm),
972 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
975 bits<5> Dm;
980 let Inst{3-0} = Dm{3-0};
981 let Inst{5} = Dm{4};
1025 (outs DPR:$Dd), (ins DPR:$Dm),
1026 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", "",
1027 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
1062 (outs DPR:$Dd), (ins DPR:$Dm),
1063 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", "",
1064 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
1076 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
1077 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>,
1104 (outs DPR:$Dd), (ins DPR:$Dm),
1105 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
1106 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
1118 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
1119 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,
1129 (outs DPR:$Dd), (ins DPR:$Dm),
1130 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", "",
1131 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>,
1148 (outs DPR:$Dd), (ins DPR:$Dm),
1149 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", "", []>,
1230 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1231 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1232 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
1236 bits<5> Dm;
1241 let Inst{3-0} = Dm{3-0};
1242 let Inst{5} = Dm{4};
1253 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
1254 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1287 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
1288 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
1289 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]>,
1293 bits<5> Dm;
1298 let Inst{3-0} = Dm{3-0};
1299 let Inst{5} = Dm{4};
1310 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
1576 bits<5> Dm;
1579 let Inst{3-0} = Dm{3-0};
1580 let Inst{5} = Dm{4};
1629 (outs SPR:$Sd), (ins DPR:$Dm),
1630 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1687 (outs SPR:$Sd), (ins DPR:$Dm),
1688 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1747 (outs SPR:$Sd), (ins DPR:$Dm),
1748 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1749 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
1772 (outs SPR:$Sd), (ins DPR:$Dm),
1773 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1774 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,
1799 (outs SPR:$Sd), (ins DPR:$Dm),
1800 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm",
2052 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2053 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
2054 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2093 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2094 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
2095 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
2133 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2134 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
2135 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
2185 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2186 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
2187 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2226 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2227 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
2228 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2267 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
2268 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2278 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2279 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
2280 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
2319 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
2320 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2330 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2331 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
2332 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
2368 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
2369 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2378 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
2379 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2389 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2390 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
2391 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2426 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
2427 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2436 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
2437 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2451 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
2454 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
2757 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
2758 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2761 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
2762 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2766 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;