Lines Matching full:spr
159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>,
194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>,
434 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
436 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>,
459 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
461 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>,
484 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
486 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
505 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
507 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>,
530 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
532 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>,
556 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
558 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
585 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
587 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
605 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
606 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
616 (outs), (ins SPR:$Sd, SPR:$Sm),
618 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> {
635 (outs), (ins SPR:$Sd, SPR:$Sm),
637 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
659 (outs SPR:$Sd), (ins SPR:$Sm),
661 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
682 (outs), (ins SPR:$Sd),
684 [(arm_cmpfpe0 SPR:$Sd)]> {
710 (outs), (ins SPR:$Sd),
712 [(arm_cmpfp0 SPR:$Sd)]> {
731 (outs DPR:$Dd), (ins SPR:$Sm),
733 [(set DPR:$Dd, (fpextend SPR:$Sm))]>,
750 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
752 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
776 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
783 (VCVTBHS (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>;
785 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
788 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
794 def : FP16Pat<(f16 (fpround SPR:$Sm)),
795 (COPY_TO_REGCLASS (VCVTBSH (IMPLICIT_DEF), SPR:$Sm), HPR)>;
796 def : FP16Pat<(fp_to_f16 SPR:$a),
797 (i32 (COPY_TO_REGCLASS (VCVTBSH (IMPLICIT_DEF), SPR:$a), GPR))>;
798 def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
801 SPR:$src2),
803 def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
806 SPR:$src2),
810 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
824 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
830 def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
833 SPR:$src2),
835 def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
838 SPR:$src2),
842 (outs DPR:$Dd), (ins SPR:$Sm),
858 (VCVTBHD (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>,
861 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
865 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
890 (outs DPR:$Dd), (ins SPR:$Sm),
904 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
924 (outs SPR:$Sd), (ins HPR:$Sm),
932 (outs SPR:$Sd), (ins HPR:$Sm),
940 (outs SPR:$Sd), (ins SPR:$Sm),
948 (outs SPR:$Sd), (ins SPR:$Sm),
956 (outs SPR:$Sd), (ins DPR:$Dm),
971 (outs SPR:$Sd), (ins DPR:$Dm),
998 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
1000 (!cast<Instruction>(NAME#"SS") SPR:$a),
1002 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
1004 (!cast<Instruction>(NAME#"US") SPR:$a),
1030 (outs SPR:$Sd), (ins SPR:$Sm),
1032 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
1054 (outs SPR:$Sd), (ins SPR:$Sm),
1056 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1071 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1074 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1097 (outs SPR:$Sd), (ins SPR:$Sm),
1099 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1116 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
1135 (outs SPR:$Sd), (ins SPR:$Sm),
1137 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>,
1153 (outs SPR:$Sd), (ins SPR:$Sm),
1160 (outs SPR:$Sd), (ins SPR:$Sm),
1165 (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
1180 (outs GPR:$Rt), (ins SPR:$Sn),
1182 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>,
1204 (outs SPR:$Sn), (ins GPR:$Rt),
1206 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
1259 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1283 // FMDHR: GPR -> SPR
1284 // FMDLR: GPR -> SPR
1332 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
1406 // FMRDH: SPR -> GPR
1407 // FMRDL: SPR -> GPR
1408 // FMRRS: SPR -> GPR
1409 // FMRX: SPR system reg -> GPR
1410 // FMSRR: GPR -> SPR
1475 (outs DPR:$Dd), (ins SPR:$Sm),
1484 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1491 (outs SPR:$Sd),(ins SPR:$Sm),
1503 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1509 (outs HPR:$Sd), (ins SPR:$Sm),
1518 (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;
1521 (outs DPR:$Dd), (ins SPR:$Sm),
1530 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1537 (outs SPR:$Sd), (ins SPR:$Sm),
1549 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1555 (outs HPR:$Sd), (ins SPR:$Sm),
1564 (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;
1629 (outs SPR:$Sd), (ins DPR:$Dm),
1649 (outs SPR:$Sd), (ins SPR:$Sm),
1660 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1661 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1662 def : VFPPat<(i32 (fp_to_sint_sat SPR:$a, i32)),
1663 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1665 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
1667 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1668 def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f32 SPR:$a), i32)),
1670 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1673 (outs SPR:$Sd), (ins HPR:$Sm),
1687 (outs SPR:$Sd), (ins DPR:$Dm),
1707 (outs SPR:$Sd), (ins SPR:$Sm),
1718 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1719 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1720 def : VFPPat<(i32 (fp_to_uint_sat SPR:$a, i32)),
1721 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1723 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
1725 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1726 def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f32 SPR:$a), i32)),
1728 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1731 (outs SPR:$Sd), (ins HPR:$Sm),
1747 (outs SPR:$Sd), (ins DPR:$Dm),
1749 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
1755 (outs SPR:$Sd), (ins SPR:$Sm),
1757 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>,
1763 (outs SPR:$Sd), (ins SPR:$Sm),
1772 (outs SPR:$Sd), (ins DPR:$Dm),
1774 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,
1780 (outs SPR:$Sd), (ins SPR:$Sm),
1782 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>,
1788 (outs SPR:$Sd), (ins SPR:$Sm),
1799 (outs SPR:$Sd), (ins DPR:$Dm),
1847 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1853 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1859 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1865 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1873 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1882 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1891 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1900 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1933 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1939 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1945 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1951 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1959 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1968 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1977 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1986 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
2018 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm),
2061 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2063 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2064 SPR:$Sdin))]>,
2084 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2085 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2102 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2104 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2105 SPR:$Sdin))]>,
2125 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2126 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
2142 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2144 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2145 SPR:$Sdin))]>,
2166 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
2167 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2177 def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)),
2178 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2194 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2196 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2215 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
2216 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
2235 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2237 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2238 SPR:$Sdin))]>,
2258 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2259 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
2270 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
2271 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2287 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2289 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2290 SPR:$Sdin))]>,
2310 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2311 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
2322 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
2323 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2339 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2341 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2342 SPR:$Sdin))]>,
2362 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
2363 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
2371 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
2372 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2381 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
2382 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2398 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2400 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2419 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
2420 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
2429 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
2430 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2439 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
2440 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2457 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2459 [(set (f32 SPR:$Sd),
2460 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
2651 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2654 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2691 (f32 (COPY_TO_REGCLASS (f16 (FCONSTH (vfp_f32f16imm_xform (f32 $imm)))), SPR))> {
2751 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
2756 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2760 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2765 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2770 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2772 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2780 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2782 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2784 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2786 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2788 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2790 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2800 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2811 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;