Lines Matching +full:1 +full:- +full:sd
1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
14 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
15 SDTCisSameAs<1, 2>]>;
16 def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
19 def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>;
30 def SDT_VMOVhr : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, i32>] >;
31 def SDT_VMOVrh : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisFP<1>] >;
35 //===----------------------------------------------------------------------===//
39 // 8-bit floating-point immediate encodings.
47 return ARM_AM::getFP16Imm(N->getValueAPF()) != -1;
49 APFloat InVal = N->getValueAPF();
51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
58 APFloat InVal = N->getValueAPF();
60 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
64 return ARM_AM::getFP32FP16Imm(N->getValueAPF()) != -1;
68 APFloat InVal = N->getValueAPF();
70 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
78 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
83 const auto &MO = MI.getOperand(1);
86 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
91 APFloat InVal = N->getValueAPF();
93 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
101 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
106 const auto &MO = MI.getOperand(1);
109 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
114 return cast<LoadSDNode>(N)->getAlign() >= 2;
118 return cast<LoadSDNode>(N)->getAlign() >= 4;
123 return cast<StoreSDNode>(N)->getAlign() >= 2;
128 return cast<StoreSDNode>(N)->getAlign() >= 4;
131 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
133 // source. It's encoded as "Size - fbits" where Size is the size of the
134 // fixed-point representation (32 or 16) and fbits is the value appearing
148 //===----------------------------------------------------------------------===//
152 let canFoldAsLoad = 1, isReMaterializable = 1 in {
159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
160 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>,
168 let isUnpredicable = 1 in
169 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),
170 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",
171 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>,
174 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
195 IIC_fpStore32, "vstr", "\t$Sd, $addr",
196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>,
203 let isUnpredicable = 1 in
204 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),
205 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",
206 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>,
209 def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode5fp16:$addr),
210 (VSTRH (bf16 HPR:$Sd), addrmode5fp16:$addr)> {
213 def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode3:$addr),
214 (STRH (COPY_TO_REGCLASS $Sd, GPR), addrmode3:$addr)> {
217 def : Pat<(alignedstore16 (bf16 HPR:$Sd), t2addrmode_imm12:$addr),
218 (t2STRHi12 (COPY_TO_REGCLASS $Sd, GPR), t2addrmode_imm12:$addr)> {
222 //===----------------------------------------------------------------------===//
234 let Inst{24-23} = 0b01; // Increment After
243 let Inst{24-23} = 0b01; // Increment After
244 let Inst{21} = 1; // Writeback
252 let Inst{24-23} = 0b10; // Decrement Before
253 let Inst{21} = 1; // Writeback
262 let Inst{24-23} = 0b01; // Increment After
275 let Inst{24-23} = 0b01; // Increment After
276 let Inst{21} = 1; // Writeback
288 let Inst{24-23} = 0b10; // Decrement Before
289 let Inst{21} = 1; // Writeback
301 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
302 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
304 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
313 //===----------------------------------------------------------------------===//
319 // T1 takes an optional dpr_reglist, must be '{d0-d15}' (exactly)
320 // T1 require v8-M.Main, secure state, target with 16 D registers (or with no D registers - NOP)
321 // T2 (bit 7 is 1):
322 // T2 takes a mandatory dpr_reglist, must be '{d0-d31}' (exactly)
323 // T2 require v8.1-M.Main, secure state, target with 16/32 D registers (or with no D registers - NO…
324 // (source: Arm v8-M ARM, DDI0553B.v ID16122022)
326 def VLLDM : AXSI4FR<"vlldm${p}\t$Rn, $regs", 0, 1>,
336 def VLLDM_T2 : AXSI4FR<"vlldm${p}\t$Rn, $regs", 1, 1>,
355 def VLSTM_T2 : AXSI4FR<"vlstm${p}\t$Rn, $regs", 1, 0>,
380 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
381 // pre-armv6 cores.
386 let Predicates = [HasFPRegs], hasNoSchedulingInfo = 1 in {
391 let Inst{24-23} = 0b01; // Increment After
398 let Inst{24-23} = 0b01; // Increment After
399 let Inst{21} = 1; // Writeback
405 let Inst{24-23} = 0b10; // Decrement Before
406 let Inst{21} = 1; // Writeback
412 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
421 //===----------------------------------------------------------------------===//
432 let TwoOperandAliasConstraint = "$Sn = $Sd" in
434 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
435 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
436 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>,
443 let TwoOperandAliasConstraint = "$Sn = $Sd" in
445 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
446 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
447 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
451 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
457 let TwoOperandAliasConstraint = "$Sn = $Sd" in
458 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
459 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
460 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
461 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>,
468 let TwoOperandAliasConstraint = "$Sn = $Sd" in
469 def VSUBH : AHbI<0b11100, 0b11, 1, 0,
470 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
471 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
472 [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
482 let TwoOperandAliasConstraint = "$Sn = $Sd" in
484 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
485 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
486 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
489 let TwoOperandAliasConstraint = "$Sn = $Sd" in
491 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
492 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
493 [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
503 let TwoOperandAliasConstraint = "$Sn = $Sd" in
505 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
506 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
507 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>,
514 let TwoOperandAliasConstraint = "$Sn = $Sd" in
516 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
517 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
518 [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
522 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
528 let TwoOperandAliasConstraint = "$Sn = $Sd" in
529 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
530 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
531 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
532 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>,
539 let TwoOperandAliasConstraint = "$Sn = $Sd" in
540 def VNMULH : AHbI<0b11100, 0b10, 1, 0,
541 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
542 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
543 [(set (f16 HPR:$Sd), (fneg (fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>,
548 Uses = [CPSR], AddedComplexity = 4, isUnpredicable = 1 in {
550 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
551 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
552 [(set (f16 HPR:$Sd), (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC))]>,
556 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
557 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
558 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
575 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
577 isUnpredicable = 1 in {
579 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
580 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
581 [(set (f16 HPR:$Sd), (SD (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
585 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
586 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
587 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
593 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
599 defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>;
616 (outs), (ins SPR:$Sd, SPR:$Sm),
617 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", "",
618 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> {
625 (outs), (ins HPR:$Sd, HPR:$Sm),
626 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
627 [(arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
635 (outs), (ins SPR:$Sd, SPR:$Sm),
636 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", "",
637 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
644 (outs), (ins HPR:$Sd, HPR:$Sm),
645 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
646 [(arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
649 //===----------------------------------------------------------------------===//
659 (outs SPR:$Sd), (ins SPR:$Sm),
660 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
661 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
668 (outs HPR:$Sd), (ins HPR:$Sm),
669 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",
670 [(set (f16 HPR:$Sd), (fabs (f16 HPR:$Sm)))]>;
677 let Inst{3-0} = 0b0000;
682 (outs), (ins SPR:$Sd),
683 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", "",
684 [(arm_cmpfpe0 SPR:$Sd)]> {
685 let Inst{3-0} = 0b0000;
694 (outs), (ins HPR:$Sd),
695 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
696 [(arm_cmpfpe0 (f16 HPR:$Sd))]> {
697 let Inst{3-0} = 0b0000;
705 let Inst{3-0} = 0b0000;
710 (outs), (ins SPR:$Sd),
711 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", "",
712 [(arm_cmpfp0 SPR:$Sd)]> {
713 let Inst{3-0} = 0b0000;
722 (outs), (ins HPR:$Sd),
723 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
724 [(arm_cmpfp0 (f16 HPR:$Sd))]> {
725 let Inst{3-0} = 0b0000;
740 let Inst{3-0} = Sm{4-1};
742 let Inst{15-12} = Dd{3-0};
749 // Special case encoding: bits 11-8 is 0b1011.
750 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
751 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", "",
752 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
755 bits<5> Sd;
759 let Inst{3-0} = Dm{3-0};
761 let Inst{15-12} = Sd{4-1};
762 let Inst{22} = Sd{0};
764 let Inst{27-23} = 0b11101;
765 let Inst{21-16} = 0b110111;
766 let Inst{11-8} = 0b1011;
767 let Inst{7-6} = 0b11;
774 // Between half, single and double-precision.
776 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
777 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", "",
788 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
789 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda",
810 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
811 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", "",
824 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
825 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda",
851 let Inst{3-0} = Sm{4-1};
865 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
866 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",
870 bits<5> Sd;
874 let Inst{3-0} = Dm{3-0};
876 let Inst{15-12} = Sd{4-1};
877 let Inst{22} = Sd{0};
897 let Inst{3-0} = Sm{4-1};
904 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
905 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",
908 bits<5> Sd;
912 let Inst{15-12} = Sd{4-1};
913 let Inst{22} = Sd{0};
914 let Inst{3-0} = Dm{3-0};
924 (outs SPR:$Sd), (ins HPR:$Sm),
925 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
928 let Inst{17-16} = rm;
932 (outs SPR:$Sd), (ins HPR:$Sm),
933 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),
936 let Inst{17-16} = rm;
940 (outs SPR:$Sd), (ins SPR:$Sm),
941 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
944 let Inst{17-16} = rm;
948 (outs SPR:$Sd), (ins SPR:$Sm),
949 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
952 let Inst{17-16} = rm;
955 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
956 (outs SPR:$Sd), (ins DPR:$Dm),
957 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
962 let Inst{17-16} = rm;
965 let Inst{3-0} = Dm{3-0};
967 let Inst{8} = 1;
971 (outs SPR:$Sd), (ins DPR:$Dm),
972 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
977 let Inst{17-16} = rm;
980 let Inst{3-0} = Dm{3-0};
982 let Inst{8} = 1;
1010 (!cast<Instruction>(NAME#"SD") DPR:$a),
1030 (outs SPR:$Sd), (ins SPR:$Sm),
1031 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
1032 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
1039 (outs HPR:$Sd), (ins HPR:$Sm),
1040 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
1041 [(set (f16 HPR:$Sd), (fneg (f16 HPR:$Sm)))]>;
1045 (outs HPR:$Sd), (ins HPR:$Sm),
1046 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
1047 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
1054 (outs SPR:$Sd), (ins SPR:$Sm),
1055 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", "",
1056 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1070 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),
1071 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1073 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
1074 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1081 defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
1083 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
1088 isUnpredicable = 1 in {
1090 (outs HPR:$Sd), (ins HPR:$Sm),
1091 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
1092 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
1094 let Inst{17-16} = rm;
1097 (outs SPR:$Sd), (ins SPR:$Sm),
1098 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
1099 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1101 let Inst{17-16} = rm;
1108 let Inst{17-16} = rm;
1112 def : InstAlias<!strconcat("vrint", opc, ".f16.f16\t$Sd, $Sm"),
1113 (!cast<Instruction>(NAME#"H") HPR:$Sd, HPR:$Sm), 0>,
1115 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
1116 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
1135 (outs SPR:$Sd), (ins SPR:$Sm),
1136 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", "",
1137 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>,
1141 (outs HPR:$Sd), (ins HPR:$Sm),
1142 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
1143 [(set (f16 HPR:$Sd), (fsqrt (f16 HPR:$Sm)))]>;
1146 let isMoveReg = 1 in {
1153 (outs SPR:$Sd), (ins SPR:$Sm),
1154 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", "", []>,
1158 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in {
1160 (outs SPR:$Sd), (ins SPR:$Sm),
1161 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
1165 (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
1166 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
1168 let Constraints = "$Sd = $Sda";
1174 //===----------------------------------------------------------------------===//
1175 // FP <-> GPR Copies. Int <-> FP Conversions.
1178 let isMoveReg = 1 in {
1190 let Inst{19-16} = Sn{4-1};
1192 let Inst{15-12} = Rt;
1194 let Inst{6-5} = 0b00;
1195 let Inst{3-0} = 0b0000;
1202 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1214 let Inst{19-16} = Sn{4-1};
1216 let Inst{15-12} = Rt;
1218 let Inst{6-5} = 0b00;
1219 let Inst{3-0} = 0b0000;
1241 let Inst{3-0} = Dm{3-0};
1243 let Inst{15-12} = Rt;
1244 let Inst{19-16} = Rt2;
1246 let Inst{7-6} = 0b00;
1255 let isExtractSubreg = 1;
1269 let Inst{3-0} = src1{4-1};
1271 let Inst{15-12} = Rt;
1272 let Inst{19-16} = Rt2;
1274 let Inst{7-6} = 0b00;
1283 // FMDHR: GPR -> SPR
1284 // FMDLR: GPR -> SPR
1298 let Inst{3-0} = Dm{3-0};
1300 let Inst{15-12} = Rt;
1301 let Inst{19-16} = Rt2;
1303 let Inst{7-6} = 0b00;
1311 let isRegSequence = 1;
1343 let Inst{3-0} = dst1{4-1};
1345 let Inst{15-12} = src1;
1346 let Inst{19-16} = src2;
1348 let Inst{7-6} = 0b00;
1357 // Move H->R, clearing top 16 bits
1369 let Inst{19-16} = Sn{4-1};
1371 let Inst{15-12} = Rt;
1373 let Inst{6-5} = 0b00;
1374 let Inst{3-0} = 0b0000;
1376 let isUnpredicable = 1;
1379 // Move R->H, clearing top 16 bits
1391 let Inst{19-16} = Sn{4-1};
1393 let Inst{15-12} = Rt;
1395 let Inst{6-5} = 0b00;
1396 let Inst{3-0} = 0b0000;
1398 let isUnpredicable = 1;
1406 // FMRDH: SPR -> GPR
1407 // FMRDL: SPR -> GPR
1408 // FMRRS: SPR -> GPR
1409 // FMRX: SPR system reg -> GPR
1410 // FMSRR: GPR -> SPR
1411 // FMXR: GPR -> VFP system reg
1414 // Int -> FP:
1427 let Inst{3-0} = Sm{4-1};
1429 let Inst{15-12} = Dd{3-0};
1442 bits<5> Sd;
1446 let Inst{3-0} = Sm{4-1};
1448 let Inst{15-12} = Sd{4-1};
1449 let Inst{22} = Sd{0};
1461 bits<5> Sd;
1465 let Inst{3-0} = Sm{4-1};
1467 let Inst{15-12} = Sd{4-1};
1468 let Inst{22} = Sd{0};
1479 let Inst{7} = 1; // s32
1491 (outs SPR:$Sd),(ins SPR:$Sm),
1492 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1495 let Inst{7} = 1; // s32
1509 (outs HPR:$Sd), (ins SPR:$Sm),
1510 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",
1513 let Inst{7} = 1; // s32
1514 let isUnpredicable = 1;
1537 (outs SPR:$Sd), (ins SPR:$Sm),
1538 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1555 (outs HPR:$Sd), (ins SPR:$Sm),
1556 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",
1560 let isUnpredicable = 1;
1566 // FP -> Int:
1575 bits<5> Sd;
1579 let Inst{3-0} = Dm{3-0};
1581 let Inst{15-12} = Sd{4-1};
1582 let Inst{22} = Sd{0};
1595 bits<5> Sd;
1599 let Inst{3-0} = Sm{4-1};
1601 let Inst{15-12} = Sd{4-1};
1602 let Inst{22} = Sd{0};
1614 bits<5> Sd;
1618 let Inst{3-0} = Sm{4-1};
1620 let Inst{15-12} = Sd{4-1};
1621 let Inst{22} = Sd{0};
1629 (outs SPR:$Sd), (ins DPR:$Dm),
1630 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1633 let Inst{7} = 1; // Z bit
1649 (outs SPR:$Sd), (ins SPR:$Sm),
1650 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1653 let Inst{7} = 1; // Z bit
1673 (outs SPR:$Sd), (ins HPR:$Sm),
1674 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
1677 let Inst{7} = 1; // Z bit
1678 let isUnpredicable = 1;
1687 (outs SPR:$Sd), (ins DPR:$Dm),
1688 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1691 let Inst{7} = 1; // Z bit
1707 (outs SPR:$Sd), (ins SPR:$Sm),
1708 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1711 let Inst{7} = 1; // Z bit
1731 (outs SPR:$Sd), (ins HPR:$Sm),
1732 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
1735 let Inst{7} = 1; // Z bit
1736 let isUnpredicable = 1;
1747 (outs SPR:$Sd), (ins DPR:$Dm),
1748 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1749 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
1755 (outs SPR:$Sd), (ins SPR:$Sm),
1756 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1757 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>,
1763 (outs SPR:$Sd), (ins SPR:$Sm),
1764 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1768 let isUnpredicable = 1;
1772 (outs SPR:$Sd), (ins DPR:$Dm),
1773 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1774 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,
1780 (outs SPR:$Sd), (ins SPR:$Sm),
1781 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1782 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>,
1788 (outs SPR:$Sd), (ins SPR:$Sm),
1789 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
1793 let isUnpredicable = 1;
1797 // v8.3-a Javascript Convert to Signed fixed-point
1799 (outs SPR:$Sd), (ins DPR:$Dm),
1800 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm",
1803 let Inst{7} = 1; // Z bit
1806 // Convert between floating-point and fixed-point
1807 // Data type for fixed-point naming convention:
1808 // S16 (U=0, sx=0) -> SH
1809 // U16 (U=1, sx=0) -> UH
1810 // S32 (U=0, sx=1) -> SL
1811 // U32 (U=1, sx=1) -> UL
1815 // FP to Fixed-Point:
1825 let Inst{15-12} = dst{4-1};
1838 let Inst{15-12} = dst{3-0};
1844 let isUnpredicable = 1 in {
1858 def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1,
1864 def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1,
1870 } // End of 'let isUnpredicable = 1 in'
1890 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1899 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1918 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1923 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1928 // Fixed-Point to FP:
1930 let isUnpredicable = 1 in {
1944 def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1,
1950 def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1,
1956 } // End of 'let isUnpredicable = 1 in'
1976 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1985 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
2004 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
2009 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
2016 // BFloat16 - Single precision, unary, predicated
2018 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm),
2020 opc, ".bf16.f32\t$Sd, $Sm", "", []>,
2021 RegConstraint<"$dst = $Sd">,
2024 bits<5> Sd;
2028 let Inst{3-0} = Sm{4-1};
2030 let Inst{15-12} = Sd{4-1};
2031 let Inst{22} = Sd{0};
2033 let Inst{27-23} = 0b11101; // opcode1
2034 let Inst{21-20} = 0b11; // opcode2
2035 let Inst{19-16} = 0b0011; // opcode3
2036 let Inst{11-8} = 0b1001;
2037 let Inst{7-6} = op7_6;
2047 //===----------------------------------------------------------------------===//
2048 // FP Multiply-Accumulate Operations.
2061 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2062 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
2063 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2065 RegConstraint<"$Sdin = $Sd">,
2074 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2075 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",
2076 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)),
2078 RegConstraint<"$Sdin = $Sd">,
2092 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
2101 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
2102 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2103 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
2104 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2106 RegConstraint<"$Sdin = $Sd">,
2114 def VMLSH : AHbI<0b11100, 0b00, 1, 0,
2115 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2116 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",
2117 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2119 RegConstraint<"$Sdin = $Sd">,
2132 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
2141 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
2142 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2143 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
2144 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2146 RegConstraint<"$Sdin = $Sd">,
2154 def VNMLAH : AHbI<0b11100, 0b01, 1, 0,
2155 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2156 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",
2157 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2159 RegConstraint<"$Sdin = $Sd">,
2162 // (-(a * b) - dst) -> -(dst + (a * b))
2173 // (-dst - (a * b)) -> -(dst + (a * b))
2194 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2195 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
2196 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2197 RegConstraint<"$Sdin = $Sd">,
2206 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2207 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",
2208 … [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>,
2209 RegConstraint<"$Sdin = $Sd">,
2222 //===----------------------------------------------------------------------===//
2223 // Fused FP Multiply-Accumulate Operations.
2235 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2236 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
2237 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2239 RegConstraint<"$Sdin = $Sd">,
2247 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2248 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",
2249 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)),
2251 RegConstraint<"$Sdin = $Sd">,
2266 // (fma x, y, z) -> (vfms z, x, y)
2277 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
2286 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
2287 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2288 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
2289 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2291 RegConstraint<"$Sdin = $Sd">,
2298 def VFMSH : AHbI<0b11101, 0b10, 1, 0,
2299 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2300 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
2301 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2303 RegConstraint<"$Sdin = $Sd">,
2318 // (fma (fneg x), y, z) -> (vfms z, x, y)
2329 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
2338 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
2339 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2340 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
2341 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2343 RegConstraint<"$Sdin = $Sd">,
2350 def VFNMAH : AHbI<0b11101, 0b01, 1, 0,
2351 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2352 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",
2353 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2355 RegConstraint<"$Sdin = $Sd">,
2367 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
2377 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
2398 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2399 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
2400 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2401 RegConstraint<"$Sdin = $Sd">,
2409 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2410 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
2411 … [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>,
2412 RegConstraint<"$Sdin = $Sd">,
2425 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
2435 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
2446 //===----------------------------------------------------------------------===//
2457 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2459 [(set (f32 SPR:$Sd),
2461 RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>;
2463 def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p),
2465 [(set (f16 HPR:$Sd),
2467 RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>;
2470 //===----------------------------------------------------------------------===//
2481 let Inst{27-20} = 0b11101111;
2482 let Inst{19-16} = opc19_16;
2483 let Inst{15-12} = Rt;
2484 let Inst{11-8} = 0b1010;
2486 let Inst{6-5} = 0b00;
2487 let Inst{4} = 1;
2488 let Inst{3-0} = 0b0000;
2489 let Unpredictable{7-5} = 0b111;
2490 let Unpredictable{3-0} = 0b1111;
2501 // Application level FPSCR -> GPR
2502 let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in
2507 // System level FPEXC, FPSID -> GPR
2526 // System level FPSCR_NZCVQC -> GPR
2534 // System level FPSCR -> GPR, with context saving for security extensions
2539 // System level FPSCR -> GPR, with context saving for security extensions
2545 // System level VPR/P0 -> GPR
2555 //===----------------------------------------------------------------------===//
2566 let Inst{27-20} = 0b11101110;
2567 let Inst{19-16} = opc19_16;
2568 let Inst{15-12} = Rt;
2569 let Inst{11-8} = 0b1010;
2571 let Inst{6-5} = 0b00;
2572 let Inst{4} = 1;
2573 let Inst{3-0} = 0b0000;
2575 let Unpredictable{7-5} = 0b111;
2576 let Unpredictable{3-0} = 0b1111;
2582 // Application level GPR -> FPSCR
2586 // System level GPR -> FPEXC
2589 // System level GPR -> FPSID
2598 // System level GPR -> FPSCR with context saving for security extensions
2603 // System level GPR -> FPSCR with context saving for security extensions
2608 // System level GPR -> FPSCR_NZCVQC
2616 // System level GPR -> VPR/P0
2626 //===----------------------------------------------------------------------===//
2631 let isReMaterializable = 1 in {
2640 let Inst{27-23} = 0b11101;
2642 let Inst{21-20} = 0b11;
2643 let Inst{19-16} = imm{7-4};
2644 let Inst{15-12} = Dd{3-0};
2645 let Inst{11-9} = 0b101;
2646 let Inst{8} = 1; // Double precision.
2647 let Inst{7-4} = 0b0000;
2648 let Inst{3-0} = imm{3-0};
2651 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2653 "vmov", ".f32\t$Sd, $imm", "",
2654 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2655 bits<5> Sd;
2658 let Inst{27-23} = 0b11101;
2659 let Inst{22} = Sd{0};
2660 let Inst{21-20} = 0b11;
2661 let Inst{19-16} = imm{7-4};
2662 let Inst{15-12} = Sd{4-1};
2663 let Inst{11-9} = 0b101;
2665 let Inst{7-4} = 0b0000;
2666 let Inst{3-0} = imm{3-0};
2669 def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm),
2671 "vmov", ".f16\t$Sd, $imm", "",
2672 [(set (f16 HPR:$Sd), vfp_f16imm:$imm)]>,
2674 bits<5> Sd;
2677 let Inst{27-23} = 0b11101;
2678 let Inst{22} = Sd{0};
2679 let Inst{21-20} = 0b11;
2680 let Inst{19-16} = imm{7-4};
2681 let Inst{15-12} = Sd{4-1};
2682 let Inst{11-8} = 0b1001; // Half precision
2683 let Inst{7-4} = 0b0000;
2684 let Inst{3-0} = imm{3-0};
2686 let isUnpredicable = 1;
2695 // Floating-point environment management.
2702 //===----------------------------------------------------------------------===//
2705 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
2749 // Be friendly and accept the old form of zero-compare
2755 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
2756 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2759 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
2760 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2765 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2769 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
2770 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2771 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
2772 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2778 // VMOV can accept optional 32-bit or less data type suffix suffix.
2799 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
2800 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2806 // assembler to accept encoded fp constants (but the equivalent fp-literal is
2810 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
2811 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;
2817 let Inst{31-23} = 0b111011001;
2819 let Inst{21-16} = 0b011111;
2820 let Inst{15-12} = regs{11-8};
2821 let Inst{11-8} = 0b1011;
2822 let Inst{7-1} = regs{7-1};
2834 let Inst{31-23} = 0b111011001;
2836 let Inst{21-16} = 0b011111;
2837 let Inst{15-12} = regs{12-9};
2838 let Inst{11-8} = 0b1010;
2839 let Inst{7-0} = regs{7-0};
2846 //===----------------------------------------------------------------------===//
2856 let Inst{27-25} = 0b110;
2862 let Inst{19-16} = addr{11-8};
2863 let Inst{15-13} = SysReg{2-0};
2864 let Inst{12-7} = 0b011111;
2865 let Inst{6-0} = addr{6-0};
2869 let hasSideEffects = 1;
2875 vfp_vstrldr<opc, 1, 0, SysReg, sysreg,
2882 vfp_vstrldr<opc, 1, 1, SysReg, sysreg,
2890 vfp_vstrldr<opc, 0, 1, SysReg, sysreg,
2896 let Inst{19-16} = Rn{3-0};