Lines Matching full:banked

4500 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
4501                       NoItinerary, "mrs", "\t$Rd, $banked", []>,
4503   bits<6> banked;
4507   let Inst{20} = banked{5}; // R bit
4508   let Inst{19-16} = banked{3-0};
4512   let Inst{4} = banked{4};
4557 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
4559 def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),
4560                       NoItinerary, "msr", "\t$banked, $Rn", []>,
4562   bits<6> banked;
4566   let Inst{20} = banked{5}; // R bit
4569   let Inst{11-8} = banked{3-0};
4571   let Inst{4} = banked{4};