Lines Matching +full:20 +full:w
696 let Inst{22-20} = opc22_20;
715 let Inst{22-20} = opc22_20;
795 // the ".w" suffix to indicate that they are wide.
799 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
800 // Assembler aliases w/ the ".w" suffix.
801 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
804 // Assembler aliases w/o the ".w" suffix.
813 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
831 opc, ".w\t$Rd, $Rn, $imm",
929 opc, ".w\t$Rd, $Rn, $imm",
945 opc, ".w\t$Rd, $Rn, $imm",
958 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
968 let Inst{20} = 0; // The S bit.
977 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
987 let Inst{20} = 0; // The S bit.
997 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
1012 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
1040 opc, ".w\t$Rd, $Rn, $Rm",
1054 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
1063 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
1066 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
1069 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $ShiftedRm"),
1089 opc, ".w\t$Rd, $Rm, $imm",
1101 opc, ".w\t$Rd, $Rn, $Rm",
1112 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
1115 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
1119 // Assembler aliases w/o the ".w" suffix.
1146 opc, ".w\t$Rn, $imm",
1151 let Inst{20} = 1; // The S bit.
1158 opc, ".w\t$Rn, $Rm",
1163 let Inst{20} = 1; // The S bit.
1172 opc, ".w\t$Rn, $ShiftedRm",
1178 let Inst{20} = 1; // The S bit.
1183 // Assembler aliases w/o the ".w" suffix.
1197 opc, ".w\t$Rt, $addr",
1206 let Inst{20} = 1; // load
1224 let Inst{20} = 1; // load
1231 let Inst{8} = 0; // The W bit.
1237 opc, ".w\t$Rt, $addr",
1245 let Inst{20} = 1; // load
1262 opc, ".w\t$Rt, $addr",
1270 let Inst{20} = 1; // load
1289 opc, ".w\t$Rt, $addr",
1295 let Inst{20} = 0; // !load
1313 let Inst{20} = 0; // !load
1317 let Inst{8} = 0; // The W bit.
1328 opc, ".w\t$Rt, $addr",
1334 let Inst{20} = 0; // !load
1356 let Inst{22-20} = opcod;
1367 opc, ".w\t$Rd, $Rm$rot", []>,
1371 // UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier.
1391 let Inst{22-20} = opcod;
1421 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1427 let Inst{20} = 0;
1592 // .w suffixes; Constraints can't be used on t2InstAlias to describe
1594 def t2LDR_PRE_imm : t2AsmPseudo<"ldr${p}.w $Rt, $addr!",
1596 def t2LDR_POST_imm : t2AsmPseudo<"ldr${p}.w $Rt, $Rn, $imm",
1600 // .w suffixes; Constraints can't be used on t2InstAlias to describe
1602 def t2LDRB_OFFSET_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $addr",
1604 def t2LDRB_PRE_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $addr!",
1606 def t2LDRB_POST_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $Rn, $imm",
1610 // .w suffixes; Constraints can't be used on t2InstAlias to describe
1612 def t2LDRH_OFFSET_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $addr",
1614 def t2LDRH_PRE_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $addr!",
1616 def t2LDRH_POST_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $Rn, $imm",
1620 // .w suffixes; Constraints can't be used on t2InstAlias to describe
1622 def t2LDRSB_OFFSET_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $addr",
1624 def t2LDRSB_PRE_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $addr!",
1626 def t2LDRSB_POST_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $Rn, $imm",
1630 // .w suffixes; Constraints can't be used on t2InstAlias to describe
1632 def t2LDRSH_OFFSET_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $addr",
1634 def t2LDRSH_PRE_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $addr!",
1636 def t2LDRSH_POST_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $Rn, $imm",
1651 let Inst{20} = 1; // load
1676 let Inst{23-20} = bits23_20;
1797 // .w suffixes; Constraints can't be used on t2InstAlias to describe
1800 def t2STR_PRE_imm : t2AsmPseudo<"str${p}.w $Rt, $addr!",
1802 def t2STR_POST_imm : t2AsmPseudo<"str${p}.w $Rt, $Rn, $imm",
1806 // .w suffixes; Constraints can't be used on t2InstAlias to describe
1808 def t2STRB_OFFSET_imm : t2AsmPseudo<"strb${p}.w $Rt, $addr",
1810 def t2STRB_PRE_imm : t2AsmPseudo<"strb${p}.w $Rt, $addr!",
1812 def t2STRB_POST_imm : t2AsmPseudo<"strb${p}.w $Rt, $Rn, $imm",
1816 // .w suffixes; Constraints can't be used on t2InstAlias to describe
1818 def t2STRH_OFFSET_imm : t2AsmPseudo<"strh${p}.w $Rt, $addr",
1820 def t2STRH_PRE_imm : t2AsmPseudo<"strh${p}.w $Rt, $addr!",
1822 def t2STRH_POST_imm : t2AsmPseudo<"strh${p}.w $Rt, $Rn, $imm",
1836 let Inst{20} = 0; // store
1891 let Inst{26-20} = 0b0001100;
1923 let Inst{20} = 1;
1942 let Inst{20} = 1;
1962 let Inst{20} = 1;
1979 // PLD/PLDW/PLI aliases w/ the optional .w suffix
1980 def : t2InstAlias<"pld${p}.w\t$addr",
1982 def : t2InstAlias<"pld${p}.w\t$addr",
1984 def : t2InstAlias<"pld${p}.w\t$addr",
1987 def : InstAlias<"pldw${p}.w\t$addr",
1990 def : InstAlias<"pldw${p}.w\t$addr",
1993 def : InstAlias<"pldw${p}.w\t$addr",
1997 def : InstAlias<"pli${p}.w\t$addr",
2000 def : InstAlias<"pli${p}.w\t$addr",
2003 def : InstAlias<"pli${p}.w\t$addr",
2015 let Inst{22-20} = 0b001;
2029 def : t2InstAlias<"pld${p}.w $addr",
2031 def : InstAlias<"pli${p}.w $addr",
2041 def : t2InstAlias<"pld${p}.w $addr",
2043 def : InstAlias<"pli${p}.w $addr",
2055 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
2064 let Inst{20} = L_bit;
2070 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
2079 let Inst{20} = L_bit;
2094 let Inst{20} = L_bit;
2109 let Inst{20} = L_bit;
2124 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
2133 let Inst{20} = L_bit;
2142 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
2151 let Inst{20} = L_bit;
2169 let Inst{20} = L_bit;
2187 let Inst{20} = L_bit;
2209 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
2218 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2220 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2229 "mov", ".w\t$Rd, $imm",
2240 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2245 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2258 let Inst{20} = 0; // The S bit.
2293 let Inst{20} = 0; // The S bit.
2453 def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
2455 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
2465 def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
2467 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
2531 let Inst{22-20} = 0b010;
2545 let Inst{22-20} = op22_20;
2661 let Inst{22-20} = op22_20;
2671 let Inst{22-20} = op22_20;
2699 let Inst{20} = 0;
2781 def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0",
2806 "lsrs", ".w\t$Rd, $Rm, #1",
2812 let Inst{20} = 1; // The S bit.
2821 "asrs", ".w\t$Rd, $Rm, #1",
2827 let Inst{20} = 1; // The S bit.
2879 let Inst{24-20} = 0b10110;
2894 let Inst{24-20} = 0b10100;
2905 let Inst{24-20} = 0b11100;
2912 def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
2917 let Inst{26-20} = 0b1111111;
2934 let Inst{24-20} = 0b10110;
2947 def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $imm",
2949 def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $Rm",
2951 def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $ShiftedRm",
2976 opc, ".w\t$Rd, $Rm",
2988 opc, ".w\t$Rd, $ShiftedRm",
3043 let Inst{22-20} = 0b000;
3055 let Inst{22-20} = 0b000;
3094 let Inst{22-20} = 0b101;
3112 let Inst{22-20} = op22_20;
3132 let Inst{22-20} = op22_20;
3179 let Inst{22-20} = op22_20;
3307 let Inst{20} = 0b1;
3319 let Inst{20} = 0b1;
3333 let Inst{21-20} = op1;
3350 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
3354 "rev16", ".w\t$Rd, $Rm",
3362 "revsh", ".w\t$Rd, $Rm",
3380 let Inst{24-20} = 0b01100;
3409 let Inst{24-20} = 0b01100;
3437 // + CRC32{B,H,W} 0x04C11DB7
3438 // + CRC32C{B,H,W} 0x1EDC6F41
3448 let Inst{20} = C;
3458 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
3478 "cmn", ".w\t$Rn, $imm",
3484 let Inst{20} = 1; // The S bit.
3491 "cmn", ".w\t$Rn, $Rm",
3497 let Inst{20} = 1; // The S bit.
3506 "cmn", ".w\t$Rn, $ShiftedRm",
3513 let Inst{20} = 1; // The S bit.
3518 // Assembler aliases w/o the ".w" suffix.
3656 let Inst{26-20} = 0b0001101;
3671 let Inst{26-20} = 0b0001100;
3702 let Inst{26-20} = 0b0000101;
3736 let Inst{26-20} = 0b0001101;
3783 let Inst{26-20} = 0b0000100;
3829 let Inst{26-20} = 0b0001100;
3938 "b", ".w\t$target",
3949 let Inst{25-16} = target{20-11};
3978 let Inst{31-20} = 0b111010001101;
3991 let Inst{31-20} = 0b111010001101;
4007 "b", ".w\t$target",
4017 let Inst{26} = target{20};
4065 let Inst{25-20} = 0b111100;
4070 def : t2InstAlias<"bl${p}.w $func", (tBL pred:$p, thumb_bl_target:$func), 0>;
4125 "$imod.w\t$iflags">;
4129 def : t2InstAlias<"cps$imod.w $iflags, $mode",
4131 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
4135 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
4145 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
4146 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
4147 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
4148 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
4149 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
4150 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
4153 def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
4159 def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
4160 def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>;
4174 let Inst{31-20} = 0b111100111010;
4180 def : t2InstAlias<"dbg${p}.w $opt", (t2DBG imm0_15:$opt, pred:$p), 0>;
4188 let Inst{26-20} = 0b1111111;
4198 let Inst{26-20} = 0b1111000;
4209 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
4217 let Inst{21} = W;
4218 let Inst{20-16} = 0b01101;
4246 let Inst{31-20} = op31_20{11-0};
4283 def : t2InstAlias<"movs${p}.w\tpc, lr", (t2SUBS_PC_LR 0, pred:$p)>;
4293 def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,
4296 let Inst{31-20} = 0b111101111110;
4303 // Alias for HVC without the ".w" optional width specifier
4396 let Inst{21} = 0; // W = 0
4397 let Inst{20} = load;
4413 let Inst{21} = 1; // W = 1
4414 let Inst{20} = load;
4432 let Inst{21} = 1; // W = 1
4433 let Inst{20} = load;
4451 let Inst{21} = 0; // W = 0
4452 let Inst{20} = load;
4507 let Inst{20} = banked{5}; // R bit
4530 let Unpredictable{20-16} = 0b11111;
4550 let Inst{20} = mask{4}; // R Bit
4566 let Inst{20} = banked{5}; // R bit
4586 let Inst{20} = 0b0;
4593 let Unpredictable{20} = 0b1;
4608 let Inst{20} = direction;
4633 let Inst{20} = direction;
4743 let Inst{23-20} = opc1;
4769 let Inst{23-20} = opc1;
4817 let Inst{31-20} = 0b111010000100;
4923 // Aliases for ADC without the ".w" optional width specifier.
4935 // Aliases for SBC without the ".w" optional width specifier.
4942 // Aliases for ADD without the ".w" optional width specifier.
4966 // add w/ negative immediates is just a sub.
4978 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
4983 def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",
4990 // Aliases for SUB without the ".w" optional width specifier.
5007 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
5016 // Aliases for ADD without the ".w" optional width specifier.
5026 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
5035 // add w/ negative immediates is just a sub.
5047 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
5052 def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",
5059 // Aliases for SUB without the ".w" optional width specifier.
5067 def : t2InstAlias<"sub${s}${p}.w $Rdn, $imm",
5074 // Alias for compares without the ".w" optional width specifier.
5083 def : InstAlias<"dmb${p}.w\t$opt", (t2DMB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;
5085 def : InstAlias<"dmb${p}.w", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5086 def : InstAlias<"dsb${p}.w\t$opt", (t2DSB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;
5088 def : InstAlias<"dsb${p}.w", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5089 def : InstAlias<"isb${p}.w\t$opt", (t2ISB instsyncb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;
5091 def : InstAlias<"isb${p}.w", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5114 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
5149 // Alias for MVN with(out) the ".w" optional width specifier.
5150 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
5167 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
5169 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5172 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
5178 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
5184 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
5185 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
5187 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
5190 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
5191 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
5193 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
5196 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
5202 // Alias for RSB with and without the ".w" optional width specifier, with and
5213 def : t2InstAlias<"rsb${s}${p}.w $Rdn, $Rm",
5215 def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $Rm",
5217 def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $ShiftedRm",
5227 // STM w/o the .w suffix.
5231 // Alias for STR, STRB, and STRH without the ".w" optional
5265 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
5267 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
5287 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
5289 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
5292 // Extend instruction w/o the ".w" optional width specifier.
5323 def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm",
5326 def : t2InstSubst<"bic${s}${p}.w $Rdn, $imm",
5335 def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm",
5338 def : t2InstSubst<"and${s}${p}.w $Rdn, $imm",
5396 // Aliases for the above with the .w qualifier
5397 def : t2InstAlias<"mov${p}.w $Rd, $shift",
5399 def : t2InstAlias<"movs${p}.w $Rd, $shift",
5401 def : t2InstAlias<"mov${p}.w $Rd, $shift",
5403 def : t2InstAlias<"movs${p}.w $Rd, $shift",
5406 // ADR w/o the .w suffix
5410 // LDR(literal) w/ alternate [pc, #imm] syntax.
5421 // Version w/ the .w suffix.
5422 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
5424 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
5426 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
5428 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
5430 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
5440 // Version w/ the .w suffix.
5441 def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
5491 let Inst{20-16} = label{15-11};
5521 let Inst{22-20} = 0b110;
5544 let Inst{22-20} = 0b111;
5564 let Inst{22-20} = 0b100;
5577 let Inst{22-20} = 0b100;
5692 let Inst{31-20} = 0b111010100101;
5782 let Inst{31-20} = 0b111110110110;
5797 let Inst{31-20} = 0b111110110101;