Lines Matching +full:0 +full:b00000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
33 // {5} 0 ==> lsl
35 // {4-0} imm5 shift amount.
49 ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> {
140 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095].
141 def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; }
143 return Imm >= 0 && Imm < 4096;
157 return (Val > 0 && Val < 255);
166 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
218 let PrintMethod = "printAdrLabelOperand<0>";
228 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
242 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
255 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
306 let DecoderMethod = "DecodeT2AddrModeImm7<2,0>";
451 let Inst{7-0} = imm{7-0};
465 let Inst{7-0} = imm{7-0};
477 let Inst{7-0} = imm{7-0};
488 let Inst{3-0} = ShiftedRm{3-0};
501 let Inst{3-0} = ShiftedRm{3-0};
514 let Inst{3-0} = ShiftedRm{3-0};
527 let Inst{3-0} = Rm;
537 let Inst{3-0} = Rm;
547 let Inst{3-0} = Rm;
562 let Inst{7-0} = imm{7-0};
576 let Inst{7-0} = imm{7-0};
587 let Inst{3-0} = Rm;
589 let Inst{7-6} = imm{1-0};
600 let Inst{3-0} = Rm;
602 let Inst{7-6} = imm{1-0};
614 let Inst{3-0} = Rm;
626 let Inst{3-0} = Rm;
638 let Inst{3-0} = Rm;
650 let Inst{3-0} = ShiftedRm{3-0};
665 let Inst{3-0} = ShiftedRm{3-0};
682 let Inst{3-0} = Rm;
695 let Inst{31-23} = 0b111110111;
701 let Inst{3-0} = Rm;
714 let Inst{31-23} = 0b111110111;
720 let Inst{3-0} = Rm;
729 SDPatternOperator opnode, bit Commutable = 0,
737 let Inst{31-27} = 0b11110;
738 let Inst{25} = 0;
740 let Inst{15} = 0;
748 let Inst{31-27} = 0b11101;
749 let Inst{26-25} = 0b01;
751 let Inst{15} = 0b0;
753 // architecture, bit 15 of this encoding is listed as (0) rather
754 // than 0, i.e. setting it to 1 is UNPREDICTABLE or a soft-fail
761 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1);
762 let Inst{14-12} = 0b000; // imm3
763 let Inst{7-6} = 0b00; // imm2
764 let Inst{5-4} = 0b00; // type
772 let Inst{31-27} = 0b11101;
773 let Inst{26-25} = 0b01;
775 let Inst{15} = 0;
776 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above
798 SDPatternOperator opnode, bit Commutable = 0> :
834 let Inst{31-27} = 0b11110;
835 let Inst{25} = 0;
837 let Inst{15} = 0;
845 let Inst{31-27} = 0b11101;
846 let Inst{26-25} = 0b01;
848 let Inst{14-12} = 0b000; // imm3
849 let Inst{7-6} = 0b00; // imm2
850 let Inst{5-4} = 0b00; // type
858 let Inst{31-27} = 0b11101;
859 let Inst{26-25} = 0b01;
872 bit Commutable = 0> {
922 bit Commutable = 0> {
935 let Inst{31-27} = 0b11110;
936 let Inst{25-24} = 0b01;
938 let Inst{15} = 0;
948 let Inst{31-27} = 0b11110;
949 let Inst{25} = 0;
952 let Inst{15} = 0;
964 let Inst{31-27} = 0b11110;
966 let Inst{25-24} = 0b10;
968 let Inst{20} = 0; // The S bit.
970 let Inst{15} = 0;
973 let Inst{7-0} = imm{7-0};
983 let Inst{31-27} = 0b11110;
985 let Inst{25-24} = 0b10;
987 let Inst{20} = 0; // The S bit.
989 let Inst{15} = 0;
992 let Inst{7-0} = imm{7-0};
1001 let Inst{31-27} = 0b11101;
1002 let Inst{26-25} = 0b01;
1005 let Inst{14-12} = 0b000; // imm3
1006 let Inst{7-6} = 0b00; // imm2
1007 let Inst{5-4} = 0b00; // type
1015 let Inst{31-27} = 0b11101;
1016 let Inst{26-25} = 0b01;
1026 bit Commutable = 0, bit PostISelHook = 0> {
1033 let Inst{31-27} = 0b11110;
1034 let Inst{25} = 0;
1036 let Inst{15} = 0;
1044 let Inst{31-27} = 0b11101;
1045 let Inst{26-25} = 0b01;
1047 let Inst{14-12} = 0b000; // imm3
1048 let Inst{7-6} = 0b00; // imm2
1049 let Inst{5-4} = 0b00; // type
1057 let Inst{31-27} = 0b11101;
1058 let Inst{26-25} = 0b01;
1092 let Inst{31-27} = 0b11101;
1093 let Inst{26-21} = 0b010010;
1094 let Inst{19-16} = 0b1111; // Rn
1095 let Inst{15} = 0b0;
1104 let Inst{31-27} = 0b11111;
1105 let Inst{26-23} = 0b0100;
1107 let Inst{15-12} = 0b1111;
1108 let Inst{7-4} = 0b0000;
1148 let Inst{31-27} = 0b11110;
1149 let Inst{25} = 0;
1152 let Inst{15} = 0;
1153 let Inst{11-8} = 0b1111; // Rd
1160 let Inst{31-27} = 0b11101;
1161 let Inst{26-25} = 0b01;
1164 let Inst{14-12} = 0b000; // imm3
1165 let Inst{11-8} = 0b1111; // Rd
1166 let Inst{7-6} = 0b00; // imm2
1167 let Inst{5-4} = 0b00; // type
1175 let Inst{31-27} = 0b11101;
1176 let Inst{26-25} = 0b01;
1179 let Inst{11-8} = 0b1111; // Rd
1202 let Inst{31-25} = 0b1111100;
1209 let Inst{11-0} = addr{11-0}; // imm
1219 let Inst{31-27} = 0b11111;
1220 let Inst{26-25} = 0b00;
1222 let Inst{23} = 0;
1231 let Inst{8} = 0; // The W bit.
1232 let Inst{7-0} = addr{7-0}; // imm
1240 let Inst{31-27} = 0b11111;
1241 let Inst{26-25} = 0b00;
1243 let Inst{23} = 0;
1246 let Inst{11-6} = 0b000000;
1253 let Inst{3-0} = addr{5-2}; // Rm
1254 let Inst{5-4} = addr{1-0}; // imm
1266 let Inst{31-27} = 0b11111;
1267 let Inst{26-25} = 0b00;
1271 let Inst{19-16} = 0b1111; // Rn
1274 let Inst{15-12} = Rt{3-0};
1278 let Inst{11-0} = addr{11-0};
1292 let Inst{31-27} = 0b11111;
1293 let Inst{26-23} = 0b0001;
1295 let Inst{20} = 0; // !load
1304 let Inst{11-0} = addr{11-0}; // imm
1310 let Inst{31-27} = 0b11111;
1311 let Inst{26-23} = 0b0000;
1313 let Inst{20} = 0; // !load
1317 let Inst{8} = 0; // The W bit.
1325 let Inst{7-0} = addr{7-0}; // imm
1331 let Inst{31-27} = 0b11111;
1332 let Inst{26-23} = 0b0000;
1334 let Inst{20} = 0; // !load
1335 let Inst{11-6} = 0b000000;
1342 let Inst{3-0} = addr{5-2}; // Rm
1343 let Inst{5-4} = addr{1-0}; // imm
1354 let Inst{31-27} = 0b11111;
1355 let Inst{26-23} = 0b0100;
1357 let Inst{19-16} = 0b1111; // Rn
1358 let Inst{15-12} = 0b1111;
1389 let Inst{31-27} = 0b11111;
1390 let Inst{26-23} = 0b0100;
1392 let Inst{15-12} = 0b1111;
1414 let Inst{7-0} = label{7-0};
1423 let Inst{31-27} = 0b11110;
1424 let Inst{25-24} = 0b10;
1426 let Inst{22} = 0;
1427 let Inst{20} = 0;
1428 let Inst{19-16} = 0b1111; // Rn
1429 let Inst{15} = 0;
1438 let Inst{7-0} = addr{7-0};
1443 let hasSideEffects = 0, isReMaterializable = 1 in
1459 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
1462 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1464 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1468 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1470 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1473 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1475 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1480 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1529 let mayLoad = 1, hasSideEffects = 0 in {
1530 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1536 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1542 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1548 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1554 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1560 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1566 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1572 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1578 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1584 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1589 } // mayLoad = 1, hasSideEffects = 0
1639 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1646 let Inst{31-27} = 0b11111;
1647 let Inst{26-25} = 0b00;
1649 let Inst{23} = 0;
1655 let Inst{10-8} = 0b110; // PUW.
1656 let Inst{7-0} = addr{7-0};
1661 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1662 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1663 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1664 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1665 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1674 let Inst{31-27} = 0b11101;
1675 let Inst{26-24} = 0b000;
1677 let Inst{11-6} = 0b111110;
1679 let Inst{3-0} = 0b1111;
1686 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
1689 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1692 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1697 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>;
1698 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1700 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1704 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
1705 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1713 let mayStore = 1, hasSideEffects = 0 in {
1714 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1721 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1728 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1734 } // mayStore = 1, hasSideEffects = 0
1736 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1747 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1758 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1825 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1831 let Inst{31-27} = 0b11111;
1832 let Inst{26-25} = 0b00;
1833 let Inst{24} = 0; // not signed
1834 let Inst{23} = 0;
1836 let Inst{20} = 0; // store
1838 let Inst{10-8} = 0b110; // PUW
1844 let Inst{7-0} = addr{7-0};
1847 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1848 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1849 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1853 let mayLoad = 1, hasSideEffects = 0 in
1861 let mayLoad = 1, hasSideEffects = 0 in
1862 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1867 let mayStore = 1, hasSideEffects = 0 in
1868 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1875 let mayStore = 1, hasSideEffects = 0 in
1876 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1890 let Inst{31-27} = 0b11101;
1891 let Inst{26-20} = 0b0001100;
1892 let Inst{11-6} = 0b111110;
1894 let Inst{3-0} = 0b1111;
1901 def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1903 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1905 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1910 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1918 let Inst{31-25} = 0b1111100;
1921 let Inst{22} = 0;
1924 let Inst{15-12} = 0b1111;
1928 let Inst{11-0} = addr{11-0}; // imm12
1937 let Inst{31-25} = 0b1111100;
1939 let Inst{23} = 0; // U = 0
1940 let Inst{22} = 0;
1943 let Inst{15-12} = 0b1111;
1944 let Inst{11-8} = 0b1100;
1948 let Inst{7-0} = addr{7-0}; // imm8
1957 let Inst{31-25} = 0b1111100;
1959 let Inst{23} = 0; // add = TRUE for T1
1960 let Inst{22} = 0;
1963 let Inst{15-12} = 0b1111;
1964 let Inst{11-6} = 0b000000;
1968 let Inst{3-0} = addr{5-2}; // Rm
1969 let Inst{5-4} = addr{1-0}; // imm2
1975 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1976 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1977 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1988 (t2PLDWi12 t2addrmode_imm12:$addr, pred:$p), 0>,
1991 (t2PLDWi8 t2addrmode_negimm8:$addr, pred:$p), 0>,
1994 (t2PLDWs t2addrmode_so_reg:$addr, pred:$p), 0>,
1998 (t2PLIi12 t2addrmode_imm12:$addr, pred:$p), 0>,
2001 (t2PLIi8 t2addrmode_negimm8:$addr, pred:$p), 0>,
2004 (t2PLIs t2addrmode_so_reg:$addr, pred:$p), 0>,
2012 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
2013 let Inst{31-25} = 0b1111100;
2015 let Inst{22-20} = 0b001;
2016 let Inst{19-16} = 0b1111;
2017 let Inst{15-12} = 0b1111;
2021 let Inst{11-0} = addr{11-0}; // imm12
2026 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
2032 (t2PLIpci t2ldrlabel:$addr, pred:$p), 0>,
2039 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
2044 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
2059 let Inst{31-27} = 0b11101;
2060 let Inst{26-25} = 0b00;
2061 let Inst{24-23} = 0b01; // Increment After
2062 let Inst{22} = 0;
2063 let Inst{21} = 0; // No writeback
2066 let Inst{15-0} = regs;
2074 let Inst{31-27} = 0b11101;
2075 let Inst{26-25} = 0b00;
2076 let Inst{24-23} = 0b01; // Increment After
2077 let Inst{22} = 0;
2081 let Inst{15-0} = regs;
2089 let Inst{31-27} = 0b11101;
2090 let Inst{26-25} = 0b00;
2091 let Inst{24-23} = 0b10; // Decrement Before
2092 let Inst{22} = 0;
2093 let Inst{21} = 0; // No writeback
2096 let Inst{15-0} = regs;
2104 let Inst{31-27} = 0b11101;
2105 let Inst{26-25} = 0b00;
2106 let Inst{24-23} = 0b10; // Decrement Before
2107 let Inst{22} = 0;
2111 let Inst{15-0} = regs;
2115 let hasSideEffects = 0 in {
2128 let Inst{31-27} = 0b11101;
2129 let Inst{26-25} = 0b00;
2130 let Inst{24-23} = 0b01; // Increment After
2131 let Inst{22} = 0;
2132 let Inst{21} = 0; // No writeback
2135 let Inst{15} = 0;
2137 let Inst{13} = 0;
2138 let Inst{12-0} = regs{12-0};
2146 let Inst{31-27} = 0b11101;
2147 let Inst{26-25} = 0b00;
2148 let Inst{24-23} = 0b01; // Increment After
2149 let Inst{22} = 0;
2153 let Inst{15} = 0;
2155 let Inst{13} = 0;
2156 let Inst{12-0} = regs{12-0};
2164 let Inst{31-27} = 0b11101;
2165 let Inst{26-25} = 0b00;
2166 let Inst{24-23} = 0b10; // Decrement Before
2167 let Inst{22} = 0;
2168 let Inst{21} = 0; // No writeback
2171 let Inst{15} = 0;
2173 let Inst{13} = 0;
2174 let Inst{12-0} = regs{12-0};
2182 let Inst{31-27} = 0b11101;
2183 let Inst{26-25} = 0b00;
2184 let Inst{24-23} = 0b10; // Decrement Before
2185 let Inst{22} = 0;
2189 let Inst{15} = 0;
2191 let Inst{13} = 0;
2192 let Inst{12-0} = regs{12-0};
2198 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
2207 let hasSideEffects = 0 in
2210 let Inst{31-27} = 0b11101;
2211 let Inst{26-25} = 0b01;
2212 let Inst{24-21} = 0b0010;
2213 let Inst{19-16} = 0b1111; // Rn
2214 let Inst{15} = 0b0;
2215 let Inst{14-12} = 0b000;
2216 let Inst{7-4} = 0b0000;
2231 let Inst{31-27} = 0b11110;
2232 let Inst{25} = 0;
2233 let Inst{24-21} = 0b0010;
2234 let Inst{19-16} = 0b1111; // Rn
2235 let Inst{15} = 0;
2255 let Inst{31-27} = 0b11110;
2257 let Inst{24-21} = 0b0010;
2258 let Inst{20} = 0; // The S bit.
2259 let Inst{15} = 0;
2268 let Inst{7-0} = imm{7-0};
2273 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
2287 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
2290 let Inst{31-27} = 0b11110;
2292 let Inst{24-21} = 0b0110;
2293 let Inst{20} = 0; // The S bit.
2294 let Inst{15} = 0;
2303 let Inst{7-0} = imm{7-0};
2314 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
2322 def t2SXTB : T2I_ext_rrot<0b100, "sxtb">;
2323 def t2SXTH : T2I_ext_rrot<0b000, "sxth">;
2324 def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">;
2326 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">;
2327 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">;
2328 def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">;
2341 (t2SXTB16 rGPR:$Rn, 0)>;
2343 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;
2370 def t2UXTB : T2I_ext_rrot<0b101, "uxtb">;
2371 def t2UXTH : T2I_ext_rrot<0b001, "uxth">;
2372 def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">;
2374 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF),
2376 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF),
2378 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF),
2382 (t2UXTB16 rGPR:$Rm, 0)>;
2390 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
2393 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
2397 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">;
2398 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">;
2399 def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">;
2402 0x00FF)),
2405 0xFFFF)),
2408 0xFF)),
2411 0xFFFF)),
2414 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;
2425 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
2426 defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
2441 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1, 1>;
2442 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube, 0, 1>;
2478 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;
2528 let Inst{31-27} = 0b11111;
2529 let Inst{26-24} = 0b010;
2530 let Inst{23} = 0b1;
2531 let Inst{22-20} = 0b010;
2532 let Inst{15-12} = 0b1111;
2533 let Inst{7} = 0b1;
2534 let Inst{6-4} = 0b000;
2543 let Inst{31-27} = 0b11111;
2544 let Inst{26-23} = 0b0101;
2546 let Inst{15-12} = 0b1111;
2555 let Inst{3-0} = Rm;
2569 def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>;
2570 def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>;
2571 def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>;
2572 def t2UQSUB8 : T2I_pam_intrinsics<0b100, 0b0101, "uqsub8", int_arm_uqsub8>;
2573 def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>;
2574 def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;
2575 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
2576 def t2UQADD16 : T2I_pam_intrinsics<0b001, 0b0101, "uqadd16", int_arm_uqadd16>;
2577 def t2UQADD8 : T2I_pam_intrinsics<0b000, 0b0101, "uqadd8", int_arm_uqadd8>;
2578 def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>;
2579 def t2UQSAX : T2I_pam_intrinsics<0b110, 0b0101, "uqsax", int_arm_uqsax>;
2580 def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>;
2581 def t2QADD : T2I_pam_intrinsics_rev<0b000, 0b1000, "qadd">;
2582 def t2QSUB : T2I_pam_intrinsics_rev<0b000, 0b1010, "qsub">;
2583 def t2QDADD : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">;
2584 def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">;
2624 def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>;
2625 def t2SADD16 : T2I_pam_intrinsics<0b001, 0b0000, "sadd16", int_arm_sadd16>;
2626 def t2SADD8 : T2I_pam_intrinsics<0b000, 0b0000, "sadd8", int_arm_sadd8>;
2627 def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>;
2628 def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>;
2629 def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;
2630 def t2UASX : T2I_pam_intrinsics<0b010, 0b0100, "uasx", int_arm_uasx>;
2631 def t2UADD16 : T2I_pam_intrinsics<0b001, 0b0100, "uadd16", int_arm_uadd16>;
2632 def t2UADD8 : T2I_pam_intrinsics<0b000, 0b0100, "uadd8", int_arm_uadd8>;
2633 def t2USAX : T2I_pam_intrinsics<0b110, 0b0100, "usax", int_arm_usax>;
2634 def t2USUB16 : T2I_pam_intrinsics<0b101, 0b0100, "usub16", int_arm_usub16>;
2635 def t2USUB8 : T2I_pam_intrinsics<0b100, 0b0100, "usub8", int_arm_usub8>;
2639 def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>;
2640 def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>;
2641 def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;
2642 def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>;
2643 def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;
2644 def t2SHSUB8 : T2I_pam_intrinsics<0b100, 0b0010, "shsub8", int_arm_shsub8>;
2645 def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>;
2646 def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>;
2647 def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>;
2648 def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>;
2649 def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>;
2650 def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>;
2658 let Inst{31-27} = 0b11111;
2659 let Inst{26-24} = 0b011;
2668 let Inst{31-27} = 0b11111;
2669 let Inst{26-24} = 0b011;
2676 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2681 let Inst{15-12} = 0b1111;
2683 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2697 let Inst{31-24} = 0b11110011;
2699 let Inst{20} = 0;
2701 let Inst{15} = 0;
2704 let Inst{7-6} = sh{1-0};
2705 let Inst{5} = 0;
2706 let Inst{4-0} = sat_imm;
2712 let Inst{23-22} = 0b00;
2713 let Inst{5} = 0;
2719 let Inst{23-22} = 0b00;
2720 let sh = 0b100000;
2721 let Inst{4} = 0;
2727 let Inst{23-22} = 0b10;
2733 let Inst{23-22} = 0b10;
2734 let sh = 0b100000;
2735 let Inst{4} = 0;
2739 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2741 (t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2743 (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
2745 (t2USAT imm0_31:$pos, GPR:$a, 0)>;
2772 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
2773 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
2774 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>;
2775 defm t2ROR : T2I_sh_ir<0b11, "ror", imm1_31, rotr>;
2777 // LSL #0 is actually MOV, and has slightly different permitted registers to
2779 def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0",
2781 def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0",
2784 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2792 let Inst{31-27} = 0b11101;
2793 let Inst{26-25} = 0b01;
2794 let Inst{24-21} = 0b0010;
2795 let Inst{19-16} = 0b1111; // Rn
2796 let Inst{15} = 0b0;
2797 let Unpredictable{15} = 0b1;
2798 let Inst{14-12} = 0b000;
2799 let Inst{7-4} = 0b0011;
2809 let Inst{31-27} = 0b11101;
2810 let Inst{26-25} = 0b01;
2811 let Inst{24-21} = 0b0010;
2813 let Inst{19-16} = 0b1111; // Rn
2814 let Inst{5-4} = 0b01; // Shift type.
2816 let Inst{14-12} = 0b000;
2817 let Inst{7-6} = 0b01;
2824 let Inst{31-27} = 0b11101;
2825 let Inst{26-25} = 0b01;
2826 let Inst{24-21} = 0b0010;
2828 let Inst{19-16} = 0b1111; // Rn
2829 let Inst{5-4} = 0b10; // Shift type.
2831 let Inst{14-12} = 0b000;
2832 let Inst{7-6} = 0b01;
2840 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2842 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2844 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2847 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2859 let Inst{4-0} = msb{4-0};
2861 let Inst{7-6} = lsb{1-0};
2876 let Inst{31-27} = 0b11110;
2877 let Inst{26} = 0; // should be 0.
2879 let Inst{24-20} = 0b10110;
2880 let Inst{19-16} = 0b1111; // Rn
2881 let Inst{15} = 0;
2882 let Inst{5} = 0; // should be 0.
2885 let msb{4-0} = imm{9-5};
2886 let lsb{4-0} = imm{4-0};
2892 let Inst{31-27} = 0b11110;
2894 let Inst{24-20} = 0b10100;
2895 let Inst{15} = 0;
2897 let hasSideEffects = 0;
2903 let Inst{31-27} = 0b11110;
2905 let Inst{24-20} = 0b11100;
2906 let Inst{15} = 0;
2908 let hasSideEffects = 0;
2915 let Inst{31-29} = 0b111;
2916 let Inst{28-27} = 0b10;
2917 let Inst{26-20} = 0b1111111;
2919 let Inst{15} = 0b1;
2920 let Inst{14-12} = 0b010;
2921 let Inst{11-0} = imm16{11-0};
2931 let Inst{31-27} = 0b11110;
2932 let Inst{26} = 0; // should be 0.
2934 let Inst{24-20} = 0b10110;
2935 let Inst{15} = 0;
2936 let Inst{5} = 0; // should be 0.
2939 let msb{4-0} = imm{9-5};
2940 let lsb{4-0} = imm{4-0};
2944 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2946 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2960 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2968 let Inst{31-27} = 0b11110;
2969 let Inst{25} = 0;
2971 let Inst{19-16} = 0b1111; // Rn
2972 let Inst{15} = 0;
2978 let Inst{31-27} = 0b11101;
2979 let Inst{26-25} = 0b01;
2981 let Inst{19-16} = 0b1111; // Rn
2982 let Inst{14-12} = 0b000; // imm3
2983 let Inst{7-6} = 0b00; // imm2
2984 let Inst{5-4} = 0b00; // type
2991 let Inst{31-27} = 0b11101;
2992 let Inst{26-25} = 0b01;
2994 let Inst{19-16} = 0b1111; // Rn
3000 defm t2MVN : T2I_un_irs <0b0011, "mvn",
3041 let Inst{31-27} = 0b11111;
3042 let Inst{26-23} = 0b0110;
3043 let Inst{22-20} = 0b000;
3044 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
3045 let Inst{7-4} = 0b0000; // Multiply
3053 let Inst{31-27} = 0b11111;
3054 let Inst{26-23} = 0b0110;
3055 let Inst{22-20} = 0b000;
3059 def t2MLA : T2FourRegMLA<0b0000, "mla",
3062 def t2MLS: T2FourRegMLA<0b0001, "mls",
3067 let hasSideEffects = 0 in {
3069 def t2SMULL : T2MulLong<0b000, 0b0000, "smull",
3072 def t2UMULL : T2MulLong<0b010, 0b0000, "umull",
3078 def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
3079 def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
3080 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
3092 let Inst{31-27} = 0b11111;
3093 let Inst{26-23} = 0b0110;
3094 let Inst{22-20} = 0b101;
3095 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
3098 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
3101 T2SMMUL<0b0001, "smmulr",
3102 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))]>;
3110 let Inst{31-27} = 0b11111;
3111 let Inst{26-23} = 0b0110;
3116 def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
3118 def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar",
3120 def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
3121 def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr",
3130 let Inst{31-27} = 0b11111;
3131 let Inst{26-23} = 0b0110;
3133 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
3134 let Inst{7-6} = 0b00;
3138 def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
3140 def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
3142 def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
3144 def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
3146 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",
3148 def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt",
3177 let Inst{31-27} = 0b11111;
3178 let Inst{26-23} = 0b0110;
3180 let Inst{7-6} = 0b00;
3184 def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb",
3186 def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt",
3188 def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",
3190 def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",
3192 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
3194 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
3223 def t2SMLALBB : T2MlaLong<0b100, 0b1000, "smlalbb">,
3225 def t2SMLALBT : T2MlaLong<0b100, 0b1001, "smlalbt">,
3227 def t2SMLALTB : T2MlaLong<0b100, 0b1010, "smlaltb">,
3229 def t2SMLALTT : T2MlaLong<0b100, 0b1011, "smlaltt">,
3243 : T2ThreeReg_mac<0, op22_20, op7_4,
3250 let Inst{15-12} = 0b1111;
3254 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>;
3255 def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx", int_arm_smuadx>;
3256 def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd", int_arm_smusd>;
3257 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>;
3261 : T2FourReg_mac<0, op22_20, op7_4,
3268 def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad", int_arm_smlad>;
3269 def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx", int_arm_smladx>;
3270 def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd", int_arm_smlsd>;
3271 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>;
3282 def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
3283 def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
3284 def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
3285 def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
3305 let Inst{31-27} = 0b11111;
3306 let Inst{26-21} = 0b011100;
3307 let Inst{20} = 0b1;
3308 let Inst{15-12} = 0b1111;
3309 let Inst{7-4} = 0b1111;
3317 let Inst{31-27} = 0b11111;
3318 let Inst{26-21} = 0b011101;
3319 let Inst{20} = 0b1;
3320 let Inst{15-12} = 0b1111;
3321 let Inst{7-4} = 0b1111;
3331 let Inst{31-27} = 0b11111;
3332 let Inst{26-22} = 0b01010;
3334 let Inst{15-12} = 0b1111;
3335 let Inst{7-6} = 0b10;
3337 let Rn{3-0} = Rm;
3340 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3344 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3349 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3353 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3361 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3367 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
3373 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
3375 0xFFFF0000)))]>,
3378 let Inst{31-27} = 0b11101;
3379 let Inst{26-25} = 0b01;
3380 let Inst{24-20} = 0b01100;
3381 let Inst{5} = 0; // BT form
3382 let Inst{4} = 0;
3386 let Inst{7-6} = sh{1-0};
3390 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
3391 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
3393 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
3402 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
3404 0xFFFF)))]>,
3407 let Inst{31-27} = 0b11101;
3408 let Inst{26-25} = 0b01;
3409 let Inst{24-20} = 0b01100;
3411 let Inst{4} = 0;
3415 let Inst{7-6} = sh{1-0};
3419 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3422 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
3425 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
3428 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
3429 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
3437 // + CRC32{B,H,W} 0x04C11DB7
3438 // + CRC32C{B,H,W} 0x1EDC6F41
3446 let Inst{31-27} = 0b11111;
3447 let Inst{26-21} = 0b010110;
3449 let Inst{15-12} = 0b1111;
3450 let Inst{7-6} = 0b10;
3454 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3455 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3456 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
3457 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
3458 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
3459 def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
3464 defm t2CMP : T2I_cmp_irs<0b1101, "cmp", GPRnopc,
3481 let Inst{31-27} = 0b11110;
3482 let Inst{25} = 0;
3483 let Inst{24-21} = 0b1000;
3485 let Inst{15} = 0;
3486 let Inst{11-8} = 0b1111; // Rd
3494 let Inst{31-27} = 0b11101;
3495 let Inst{26-25} = 0b01;
3496 let Inst{24-21} = 0b1000;
3498 let Inst{14-12} = 0b000; // imm3
3499 let Inst{11-8} = 0b1111; // Rd
3500 let Inst{7-6} = 0b00; // imm2
3501 let Inst{5-4} = 0b00; // type
3510 let Inst{31-27} = 0b11101;
3511 let Inst{26-25} = 0b01;
3512 let Inst{24-21} = 0b1000;
3514 let Inst{11-8} = 0b1111; // Rd
3532 defm t2TST : T2I_cmp_irs<0b0000, "tst", rGPR,
3534 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3535 defm t2TEQ : T2I_cmp_irs<0b0100, "teq", rGPR,
3537 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3540 let hasSideEffects = 0 in {
3615 let Inst{31-4} = 0xf3bf8f5;
3616 let Inst{3-0} = opt;
3623 let Inst{31-4} = 0xf3bf8f4;
3624 let Inst{3-0} = opt;
3631 let Inst{31-4} = 0xf3bf8f6;
3632 let Inst{3-0} = opt;
3638 let Inst{31-0} = 0xf3af8012;
3646 let Inst{31-0} = 0xf3bf8f70;
3647 let Unpredictable = 0x000f2f0f;
3653 list<dag> pattern, bits<4> rt2 = 0b1111>
3655 let Inst{31-27} = 0b11101;
3656 let Inst{26-20} = 0b0001101;
3659 let Inst{3-0} = 0b1111;
3668 list<dag> pattern, bits<4> rt2 = 0b1111>
3670 let Inst{31-27} = 0b11101;
3671 let Inst{26-20} = 0b0001100;
3678 let Inst{3-0} = Rd;
3684 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3689 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3701 let Inst{31-27} = 0b11101;
3702 let Inst{26-20} = 0b0000101;
3705 let Inst{11-8} = 0b1111;
3706 let Inst{7-0} = addr{7-0};
3709 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3718 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3723 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3735 let Inst{31-27} = 0b11101;
3736 let Inst{26-20} = 0b0001101;
3739 let Inst{11-8} = 0b1111;
3740 let Inst{7-0} = 0b11101111;
3743 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3757 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3764 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3782 let Inst{31-27} = 0b11101;
3783 let Inst{26-20} = 0b0000100;
3787 let Inst{7-0} = addr{7-0};
3790 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3799 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3808 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3828 let Inst{31-27} = 0b11101;
3829 let Inst{26-20} = 0b0001100;
3832 let Inst{11-4} = 0b11111110;
3833 let Inst{3-0} = Rd;
3836 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3849 let Inst{31-16} = 0xf3bf;
3850 let Inst{15-14} = 0b10;
3851 let Inst{13} = 0;
3852 let Inst{12} = 0;
3853 let Inst{11-8} = 0b1111;
3854 let Inst{7-4} = 0b0010;
3855 let Inst{3-0} = 0b1111;
3858 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3861 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3864 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3867 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3871 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
3874 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
3877 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3880 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3887 // address and save #0 in R0 for the non-longjmp case.
3904 AddrModeNone, 0, NoItinerary, "", "",
3915 AddrModeNone, 0, NoItinerary, "", "",
3941 let Inst{31-27} = 0b11110;
3942 let Inst{15-14} = 0b10;
3950 let Inst{10-0} = target{10-0};
3961 0, IIC_Br,
3967 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3971 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3978 let Inst{31-20} = 0b111010001101;
3980 let Inst{15-5} = 0b11110000000;
3981 let Inst{4} = 0; // B form
3982 let Inst{3-0} = Rm;
3991 let Inst{31-20} = 0b111010001101;
3993 let Inst{15-5} = 0b11110000000;
3995 let Inst{3-0} = Rm;
4009 let Inst{31-27} = 0b11110;
4010 let Inst{15-14} = 0b10;
4011 let Inst{12} = 0;
4021 let Inst{10-0} = target{11-1};
4046 let Inst{31-16} = 0x0000;
4047 let Inst{15-8} = 0b10111111;
4052 let Inst{3-0} = mask;
4063 let Inst{31-27} = 0b11110;
4064 let Inst{26} = 0;
4065 let Inst{25-20} = 0b111100;
4067 let Inst{15-0} = 0b1000111100000000;
4070 def : t2InstAlias<"bl${p}.w $func", (tBL pred:$p, thumb_bl_target:$func), 0>;
4076 T1Misc<{0,0,?,1,?,?,?}>,
4082 let Inst{7-3} = target{4-0};
4083 let Inst{2-0} = Rn;
4088 T1Misc<{1,0,?,1,?,?,?}>,
4094 let Inst{7-3} = target{4-0};
4095 let Inst{2-0} = Rn;
4112 let Inst{31-11} = 0b111100111010111110000;
4116 let Inst{4-0} = mode;
4123 let mode = 0, M = 0 in
4126 let imod = 0, iflags = 0, M = 1 in
4130 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
4131 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
4138 let Inst{31-3} = 0b11110011101011111000000000000;
4139 let Inst{7-0} = imm;
4144 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
4145 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
4156 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
4159 def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
4168 def : InstAlias<"clrbhb$p", (t2HINT 22, pred:$p), 0>, Requires<[IsThumb2, HasV8]>;
4174 let Inst{31-20} = 0b111100111010;
4175 let Inst{19-16} = 0b1111;
4176 let Inst{15-8} = 0b10000000;
4177 let Inst{7-4} = 0b1111;
4178 let Inst{3-0} = opt;
4180 def : t2InstAlias<"dbg${p}.w $opt", (t2DBG imm0_15:$opt, pred:$p), 0>;
4187 let Inst{31-27} = 0b11110;
4188 let Inst{26-20} = 0b1111111;
4189 let Inst{15-12} = 0b1000;
4197 let Inst{31-27} = 0b11110;
4198 let Inst{26-20} = 0b1111000;
4199 let Inst{19-16} = 0b1111;
4200 let Inst{15-12} = 0b1000;
4201 let Inst{11-2} = 0b0000000000;
4202 let Inst{1-0} = opt;
4205 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
4206 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
4207 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
4214 let Inst{31-25} = 0b1110100;
4216 let Inst{22} = 0;
4218 let Inst{20-16} = 0b01101;
4219 let Inst{15-5} = 0b11000000000;
4220 let Inst{4-0} = mode{4-0};
4224 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
4226 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
4228 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
4230 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
4246 let Inst{31-20} = op31_20{11-0};
4250 let Inst{15-0} = 0xc000;
4253 def t2RFEDBW : T2RFE<0b111010000011,
4256 def t2RFEDB : T2RFE<0b111010000001,
4259 def t2RFEIAW : T2RFE<0b111010011011,
4262 def t2RFEIA : T2RFE<0b111010011001,
4273 let Inst{31-8} = 0b111100111101111010001111;
4276 let Inst{7-0} = imm;
4281 // for SUBS{<c>}{<q>} PC, LR, #0.
4282 def : t2InstAlias<"movs${p}\tpc, lr", (t2SUBS_PC_LR 0, pred:$p)>;
4283 def : t2InstAlias<"movs${p}.w\tpc, lr", (t2SUBS_PC_LR 0, pred:$p)>;
4286 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
4288 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
4296 let Inst{31-20} = 0b111101111110;
4298 let Inst{15-12} = 0b1000;
4299 let Inst{11-0} = imm16{11-0};
4383 let Inst{27-25} = 0b110;
4396 let Inst{21} = 0; // W = 0
4401 let Inst{7-0} = addr{7-0};
4418 let Inst{7-0} = addr{7-0};
4429 let Inst{24} = 0; // P = 0
4437 let Inst{7-0} = offset{7-0};
4448 let Inst{24} = 0; // P = 0
4451 let Inst{21} = 0; // W = 0
4456 let Inst{7-0} = option;
4462 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]…
4463 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr…
4464 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr…
4465 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$ad…
4467 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]…
4468 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr…
4469 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr…
4470 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$ad…
4485 let Inst{31-12} = 0b11110011111011111000;
4487 let Inst{7-0} = 0b00000000;
4495 let Inst{31-12} = 0b11110011111111111000;
4497 let Inst{7-0} = 0b00000000;
4506 let Inst{31-21} = 0b11110011111;
4508 let Inst{19-16} = banked{3-0};
4509 let Inst{15-12} = 0b1000;
4511 let Inst{7-5} = 0b001;
4513 let Inst{3-0} = 0b0000;
4519 // This MRS has a mask field in bits 7-0 and can take more values than
4526 let Inst{31-12} = 0b11110011111011111000;
4528 let Inst{7-0} = SYSm;
4530 let Unpredictable{20-16} = 0b11111;
4531 let Unpredictable{13} = 0b1;
4541 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4549 let Inst{31-21} = 0b11110011100;
4552 let Inst{15-12} = 0b1000;
4553 let Inst{11-8} = mask{3-0};
4554 let Inst{7-0} = 0;
4565 let Inst{31-21} = 0b11110011100;
4568 let Inst{15-12} = 0b1000;
4569 let Inst{11-8} = banked{3-0};
4570 let Inst{7-5} = 0b001;
4572 let Inst{3-0} = 0b0000;
4585 let Inst{31-21} = 0b11110011100;
4586 let Inst{20} = 0b0;
4588 let Inst{15-12} = 0b1000;
4590 let Inst{9-8} = 0b00;
4591 let Inst{7-0} = SYSm{7-0};
4593 let Unpredictable{20} = 0b1;
4594 let Unpredictable{13} = 0b1;
4595 let Unpredictable{9-8} = 0b11;
4607 let Inst{27-24} = 0b1110;
4622 let Inst{3-0} = CRm;
4631 let Inst{27-24} = 0b1100;
4632 let Inst{23-21} = 0b010;
4645 let Inst{3-0} = CRm;
4651 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
4660 c_imm:$CRm, 0, pred:$p)>;
4661 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
4670 c_imm:$CRm, 0, pred:$p)>;
4673 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4678 c_imm:$CRm, 0, pred:$p)>;
4680 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4687 c_imm:$CRm, 0, pred:$p)>;
4697 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),
4702 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs),
4711 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4714 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),
4723 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4728 let Inst{27-24} = 0b1110;
4737 let Inst{3-0} = CRm;
4738 let Inst{4} = 0;
4749 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4754 let Inst{27-24} = 0b1110;
4763 let Inst{3-0} = CRm;
4764 let Inst{4} = 0;
4777 def : T2Pat<(ARMthread_pointer), (t2MRC 15, 0, 13, 0, 2)>,
4779 def : T2Pat<(ARMthread_pointer), (t2MRC 15, 0, 13, 0, 3)>,
4781 def : T2Pat<(ARMthread_pointer), (t2MRC 15, 0, 13, 0, 4)>,
4790 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4793 let Inst{4} = 0b1;
4795 let Inst{2-0} = 0b000;
4797 let Unpredictable{4} = 0b1;
4798 let Unpredictable{2-0} = 0b111;
4808 let Inst = 0xe97fe97f;
4817 let Inst{31-20} = 0b111010000100;
4819 let Inst{15-12} = 0b1111;
4822 let Inst{5-0} = 0b000000;
4824 let Unpredictable{5-0} = 0b111111;
4827 def t2TT : T2TT<0b00, "tt",
4830 def t2TTT : T2TT<0b01, "ttt",
4833 def t2TTA : T2TT<0b10, "tta",
4836 def t2TTAT : T2TT<0b11, "ttat",
4846 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4848 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4850 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4852 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4853 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4855 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4856 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4860 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4862 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4865 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4868 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
5083 def : InstAlias<"dmb${p}.w\t$opt", (t2DMB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;
5084 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5085 def : InstAlias<"dmb${p}.w", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5086 def : InstAlias<"dsb${p}.w\t$opt", (t2DSB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;
5087 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5088 def : InstAlias<"dsb${p}.w", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5089 def : InstAlias<"isb${p}.w\t$opt", (t2ISB instsyncb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;
5090 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5091 def : InstAlias<"isb${p}.w", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
5095 def : InstAlias<"ssbb", (t2DSB 0x0, 14, zero_reg), 1>, Requires<[HasDB, IsThumb2]>;
5096 def : InstAlias<"pssbb", (t2DSB 0x4, 14, zero_reg), 1>, Requires<[HasDB, IsThumb2]>;
5099 def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;
5160 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5163 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
5223 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
5225 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
5249 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5252 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5255 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5258 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
5262 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5264 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5266 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5268 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5271 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5274 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5277 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5280 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
5284 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5286 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5288 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5290 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5296 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
5304 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
5378 // "neg" is and alias for "rsb rd, rn, #0"
5380 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
5384 // FIXME: LSL #0 in the shift should allow SP to be used as either the
5423 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
5460 let Inst{31-16} = 0b1110100010011111;
5462 let Inst{13} = 0b0;
5463 let Inst{12-0} = regs{12-0};
5469 let Inst{31-27} = 0b11110;
5470 let Inst{15-14} = 0b11;
5471 let Inst{12} = 0b0;
5472 let Inst{0} = 0b1;
5478 : t2PseudoInst<(outs ), (ins pclabel:$cp), 0, NoItinerary, []> {
5489 let Inst{26-23} = b_label{3-0};
5490 let Inst{22-21} = 0b10;
5492 let Inst{13} = 0b1;
5493 let Inst{11} = label{0};
5505 let Inst{26-23} = b_label{3-0};
5506 let Inst{22} = 0b0;
5507 let Inst{21-18} = bcond{3-0};
5508 let Inst{17} = ba_label{0};
5510 let Inst{13} = 0b1;
5511 let Inst{11} = label{0};
5520 let Inst{26-23} = b_label{3-0};
5521 let Inst{22-20} = 0b110;
5522 let Inst{19-16} = Rn{3-0};
5523 let Inst{13-1} = 0b1000000000000;
5531 let Inst{26-23} = b_label{3-0};
5533 let Inst{13} = 0b0;
5534 let Inst{11} = label{0};
5543 let Inst{26-23} = b_label{3-0};
5544 let Inst{22-20} = 0b111;
5545 let Inst{19-16} = Rn{3-0};
5546 let Inst{13-1} = 0b1000000000000;
5551 let Inst{31-23} = 0b111100000;
5552 let Inst{15-14} = 0b11;
5553 let Inst{0} = 0b1;
5564 let Inst{22-20} = 0b100;
5565 let Inst{19-16} = Rn{3-0};
5566 let Inst{13-12} = 0b00;
5567 let Inst{11} = label{0};
5577 let Inst{22-20} = 0b100;
5578 let Inst{19-16} = Rn{3-0};
5579 let Inst{13-1} = 0b1000000000000;
5587 let Inst{22-16} = 0b0001111;
5588 let Inst{13-12} = 0b00;
5589 let Inst{11} = label{0};
5598 let Inst{22-16} = 0b0101111;
5599 let Inst{13-12} = 0b00;
5600 let Inst{11} = label{0};
5633 let hasSideEffects = 0 in
5692 let Inst{31-20} = 0b111010100101;
5693 let Inst{19-16} = Rn{3-0};
5695 let Inst{11-8} = Rd{3-0};
5696 let Inst{7-4} = fcond{3-0};
5697 let Inst{3-0} = Rm{3-0};
5700 let hasSideEffects = 0;
5703 def t2CSEL : CS<"csel", 0b1000>;
5704 def t2CSINC : CS<"csinc", 0b1001>;
5705 def t2CSINV : CS<"csinv", 0b1010>;
5706 def t2CSNEG : CS<"csneg", 0b1011>;
5717 def : T2Pat<(Node (i32 0), GPRwithZR:$fval, imm0_31:$imm),
5719 def : T2Pat<(Node GPRwithZR:$tval, (i32 0), imm0_31:$imm),
5721 def : T2Pat<(Node (i32 0), (i32 0), imm0_31:$imm),
5729 def : T2Pat<(ARMcmov (i32 1), (i32 0), cmovpred:$imm),
5731 def : T2Pat<(ARMcmov (i32 -1), (i32 0), cmovpred:$imm),
5733 def : T2Pat<(ARMcmov (i32 0), (i32 1), cmovpred:$imm),
5735 def : T2Pat<(ARMcmov (i32 0), (i32 -1), cmovpred:$imm),
5747 defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>;
5751 def : T2Pat<(and (topbitsallzero32:$Rn), (ARMcsinc_su (i32 0), (i32 0), cmovpred:$imm)),
5782 let Inst{31-20} = 0b111110110110;
5784 let Inst{15-12} = 0b1111;
5786 let Inst{7-4} = 0b0000;
5787 let Inst{3-0} = Rm;
5797 let Inst{31-20} = 0b111110110101;
5800 let Inst{11-5} = 0b1111000;
5802 let Inst{3-0} = Rm;
5807 "autg${p}", 0>;
5819 let Inst{31-8} = 0b111100111010111110000000;
5820 let Inst{7-0} = imm;
5822 let Unpredictable{19-16} = 0b1111;
5823 let Unpredictable{13-11} = 0b101;
5842 def t2PAC : PACBTIHintSpaceDefInst<"pac", 0b00011101>;
5843 def t2PACBTI : PACBTIHintSpaceDefInst<"pacbti", 0b00001101>;
5844 def t2BTI : PACBTIHintSpaceNoOpsInst<"bti", 0b00001111>;
5845 def t2AUT : PACBTIHintSpaceUseInst<"aut", 0b00101101> {