Lines Matching +full:21 +full:b0000
951 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
952 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
953 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
970 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
971 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
972 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
1060 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1125 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
2089 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
2090 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
2091 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
2108 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
2109 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
2110 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
2180 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
2231 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
4034 let Inst{21-19} = 0b001; // imm6 = 001xxx
4038 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4042 let Inst{21} = 0b1; // imm6 = 1xxxxx
4051 let Inst{21-19} = 0b001; // imm6 = 001xxx
4055 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4059 let Inst{21} = 0b1; // imm6 = 1xxxxx
4071 let Inst{21-19} = 0b001; // imm6 = 001xxx
4075 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4079 let Inst{21} = 0b1; // imm6 = 1xxxxx
4088 let Inst{21-19} = 0b001; // imm6 = 001xxx
4092 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4096 let Inst{21} = 0b1; // imm6 = 1xxxxx
4110 let Inst{21-19} = 0b001; // imm6 = 001xxx
4114 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4118 let Inst{21} = 0b1; // imm6 = 1xxxxx
4127 let Inst{21-19} = 0b001; // imm6 = 001xxx
4131 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4135 let Inst{21} = 0b1; // imm6 = 1xxxxx
4150 let Inst{21-19} = 0b001; // imm6 = 001xxx
4154 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4158 let Inst{21} = 0b1; // imm6 = 1xxxxx
4167 let Inst{21-19} = 0b001; // imm6 = 001xxx
4171 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4175 let Inst{21} = 0b1; // imm6 = 1xxxxx
4186 let Inst{21-19} = 0b001; // imm6 = 001xxx
4190 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4194 let Inst{21} = 0b1; // imm6 = 1xxxxx
4203 let Inst{21-19} = 0b001; // imm6 = 001xxx
4207 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4211 let Inst{21} = 0b1; // imm6 = 1xxxxx
4225 let Inst{21-19} = 0b001; // imm6 = 001xxx
4229 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4233 let Inst{21} = 0b1; // imm6 = 1xxxxx
4245 let Inst{21-19} = 0b001; // imm6 = 001xxx
4250 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4255 let Inst{21} = 0b1; // imm6 = 1xxxxx
4279 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4281 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4287 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
4290 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4301 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4304 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4484 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4960 let Inst{21-20} = rot;
4972 let Inst{21-20} = rot;
5970 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",
5972 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",
5987 let Inst{21-16} = op21_16;
6364 let Inst{21} = lane{2};
6372 let Inst{21} = lane{1};
6380 let Inst{21} = lane{2};
6388 let Inst{21} = lane{1};
6397 let Inst{21} = lane{0};
6522 let Inst{21} = lane{2};
6530 let Inst{21} = lane{1};
6539 let Inst{21} = lane{0};