Lines Matching +full:1 +full:- +full:lane
1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific Operands.
16 //===----------------------------------------------------------------------===//
115 return ((uint64_t)Imm) < 1;
256 // Register list of one D register, with byte lane subscripting.
266 // ...with half-word lane subscripting.
276 // ...with word lane subscripting.
287 // Register list of two D registers with byte lane subscripting.
297 // ...with half-word lane subscripting.
307 // ...with word lane subscripting.
317 // Register list of two Q registers with half-word lane subscripting.
327 // ...with word lane subscripting.
339 // Register list of three D registers with byte lane subscripting.
349 // ...with half-word lane subscripting.
359 // ...with word lane subscripting.
369 // Register list of three Q registers with half-word lane subscripting.
379 // ...with word lane subscripting.
390 // Register list of four D registers with byte lane subscripting.
400 // ...with half-word lane subscripting.
410 // ...with word lane subscripting.
420 // Register list of four Q registers with half-word lane subscripting.
430 // ...with word lane subscripting.
442 return cast<LoadSDNode>(N)->getAlign() >= 8;
446 return cast<StoreSDNode>(N)->getAlign() >= 8;
449 return cast<LoadSDNode>(N)->getAlign() == 4;
453 return cast<StoreSDNode>(N)->getAlign() == 4;
456 return cast<LoadSDNode>(N)->getAlign() == 2;
460 return cast<StoreSDNode>(N)->getAlign() == 2;
463 return cast<LoadSDNode>(N)->getAlign() == 1;
467 return cast<StoreSDNode>(N)->getAlign() == 1;
470 return cast<LoadSDNode>(N)->getAlign() < 4;
474 return cast<StoreSDNode>(N)->getAlign() < 4;
477 //===----------------------------------------------------------------------===//
478 // NEON-specific DAG Nodes.
479 //===----------------------------------------------------------------------===//
481 def SDTARMVTST : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
487 def SDTARMVSHXIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
489 def SDTARMVSHINSIMM : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
513 SDTypeProfile<1, 3, [SDTCisVec<0>,
514 SDTCisSameAs<0, 1>,
518 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
522 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
529 def SDTARMVTBL1 : SDTypeProfile<1, 2, [SDTCisVT<0, v8i8>, SDTCisVT<1, v8i8>,
531 def SDTARMVTBL2 : SDTypeProfile<1, 3, [SDTCisVT<0, v8i8>, SDTCisVT<1, v8i8>,
537 //===----------------------------------------------------------------------===//
539 //===----------------------------------------------------------------------===//
555 // Classes for VLD* pseudo-instructions with multi-register operands.
596 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
612 let Inst{5-4} = Rn{5-4};
617 def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>;
618 def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>;
619 def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>;
622 def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>;
623 def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>;
624 def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>;
650 let Inst{5-4} = Rn{5-4};
657 let Inst{5-4} = Rn{5-4};
663 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>;
664 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>;
665 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>;
667 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
668 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
669 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
699 def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>;
700 def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>;
701 def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>;
704 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>;
705 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>;
706 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>;
740 let Inst{5-4} = Rn{5-4};
749 let Inst{5-4} = Rn{5-4};
756 let Inst{5-4} = Rn{5-4};
762 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
763 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
764 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
767 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
768 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
769 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
797 // VLD2 : Vector Load (multiple 2-element structures)
804 let Inst{5-4} = Rn{5-4};
810 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
812 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
817 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
819 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
834 let Inst{5-4} = Rn{5-4};
841 let Inst{5-4} = Rn{5-4};
848 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
850 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
855 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
857 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
867 // ...with double-spaced registers
870 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
872 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
876 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
878 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
881 // VLD3 : Vector Load (multiple 3-element structures)
892 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
893 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
911 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
912 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
918 // ...with double-spaced registers:
920 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
921 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
923 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
924 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
939 // VLD4 : Vector Load (multiple 4-element structures)
947 let Inst{5-4} = Rn{5-4};
952 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
953 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
966 let Inst{5-4} = Rn{5-4};
971 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
972 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
978 // ...with double-spaced registers:
980 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
981 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
983 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
984 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
999 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1001 // Classes for VLD*LN pseudo-instructions with multi-register operands.
1005 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1010 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1013 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1018 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1021 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1026 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1028 // VLD1LN : Vector Load (single element to one lane)
1031 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1032 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1033 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1037 imm:$lane))]> {
1043 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1044 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1045 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1049 imm:$lane))]>, Sched<[WriteVLD1]> {
1057 imm:$lane))];
1061 let Inst{7-5} = lane{2-0};
1064 let Inst{7-6} = lane{1-0};
1065 let Inst{5-4} = Rn{5-4};
1068 let Inst{7} = lane{0};
1069 let Inst{5-4} = Rn{5-4};
1078 (f16 (load addrmode6:$addr)), imm:$lane),
1079 (VLD1LNd16 addrmode6:$addr, DPR:$src, imm:$lane)>;
1081 (f16 (load addrmode6:$addr)), imm:$lane),
1082 (VLD1LNq16Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1084 (bf16 (load addrmode6:$addr)), imm:$lane),
1085 (VLD1LNd16 addrmode6:$addr, DPR:$src, imm:$lane)>;
1087 (bf16 (load addrmode6:$addr)), imm:$lane),
1088 (VLD1LNq16Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1090 (f32 (load addrmode6:$addr)), imm:$lane),
1091 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1093 (f32 (load addrmode6:$addr)), imm:$lane),
1094 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1096 // A 64-bit subvector insert to the first 128-bit vector position
1113 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1117 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1119 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1120 "\\{$Vd[$lane]\\}, $Rn$Rm",
1126 let Inst{7-5} = lane{2-0};
1129 let Inst{7-6} = lane{1-0};
1133 let Inst{7} = lane{0};
1142 // VLD2LN : Vector Load (single 2-element structure to one lane)
1144 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1145 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1146 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1154 let Inst{7-5} = lane{2-0};
1157 let Inst{7-6} = lane{1-0};
1160 let Inst{7} = lane{0};
1167 // ...with double-spaced registers:
1168 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1169 let Inst{7-6} = lane{1-0};
1171 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1172 let Inst{7} = lane{0};
1180 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1182 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1183 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1190 let Inst{7-5} = lane{2-0};
1193 let Inst{7-6} = lane{1-0};
1196 let Inst{7} = lane{0};
1203 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1204 let Inst{7-6} = lane{1-0};
1206 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1207 let Inst{7} = lane{0};
1213 // VLD3LN : Vector Load (single 3-element structure to one lane)
1215 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1217 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1218 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1225 let Inst{7-5} = lane{2-0};
1228 let Inst{7-6} = lane{1-0};
1231 let Inst{7} = lane{0};
1238 // ...with double-spaced registers:
1239 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1240 let Inst{7-6} = lane{1-0};
1242 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1243 let Inst{7} = lane{0};
1251 : NLdStLn<1, 0b10, op11_8, op7_4,
1254 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1256 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1263 let Inst{7-5} = lane{2-0};
1266 let Inst{7-6} = lane{1-0};
1269 let Inst{7} = lane{0};
1276 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1277 let Inst{7-6} = lane{1-0};
1279 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1280 let Inst{7} = lane{0};
1286 // VLD4LN : Vector Load (single 4-element structure to one lane)
1288 : NLdStLn<1, 0b10, op11_8, op7_4,
1291 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1292 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1301 let Inst{7-5} = lane{2-0};
1304 let Inst{7-6} = lane{1-0};
1307 let Inst{7} = lane{0};
1315 // ...with double-spaced registers:
1316 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1317 let Inst{7-6} = lane{1-0};
1319 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1320 let Inst{7} = lane{0};
1329 : NLdStLn<1, 0b10, op11_8, op7_4,
1332 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1334 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1342 let Inst{7-5} = lane{2-0};
1345 let Inst{7-6} = lane{1-0};
1348 let Inst{7} = lane{0};
1356 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1357 let Inst{7-6} = lane{1-0};
1359 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1360 let Inst{7} = lane{0};
1367 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1372 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1384 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1386 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
1396 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1406 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,
1408 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
1410 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
1418 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1421 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1430 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1440 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1449 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1460 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>;
1461 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>;
1463 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>;
1464 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>;
1465 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>;
1467 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1469 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1479 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1481 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1486 // ...with double-spaced registers
1487 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1489 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1491 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1518 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1527 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1539 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes,
1541 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes,
1544 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes,
1546 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1548 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1558 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1560 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1570 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1571 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1577 // ...with double-spaced registers (not used for codegen):
1578 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1579 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1580 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1591 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1600 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>;
1601 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>;
1603 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>;
1604 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>;
1605 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>;
1615 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1617 : NLdSt<1, 0b10, 0b1111, op7_4,
1627 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1628 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1634 // ...with double-spaced registers (not used for codegen):
1635 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1636 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1637 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1648 : NLdSt<1, 0b10, 0b1111, op7_4,
1658 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1659 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1661 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1662 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1663 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1673 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1675 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
1677 // Classes for VST* pseudo-instructions with multi-register operands.
1727 let Inst{5-4} = Rn{5-4};
1732 def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>;
1733 def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>;
1734 def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>;
1737 def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>;
1738 def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>;
1739 def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>;
1766 let Inst{5-4} = Rn{5-4};
1774 let Inst{5-4} = Rn{5-4};
1780 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>;
1781 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>;
1782 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>;
1785 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
1786 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
1787 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
1804 let Inst{5-4} = Rn{5-4};
1812 let Inst{5-4} = Rn{5-4};
1818 def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>;
1819 def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>;
1820 def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>;
1823 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>;
1824 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>;
1825 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>;
1862 let Inst{5-4} = Rn{5-4};
1871 let Inst{5-4} = Rn{5-4};
1879 let Inst{5-4} = Rn{5-4};
1885 def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
1886 def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
1887 def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
1890 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1891 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1892 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
1922 // VST2 : Vector Store (multiple 2-element structures)
1928 let Inst{5-4} = Rn{5-4};
1934 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
1936 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2,
1941 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
1943 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2,
1958 let Inst{5-4} = Rn{5-4};
1965 let Inst{5-4} = Rn{5-4};
1975 let Inst{5-4} = Rn{5-4};
1983 let Inst{5-4} = Rn{5-4};
1990 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair,
1992 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair,
1996 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1997 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>;
2006 // ...with double-spaced registers
2009 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2,
2011 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2,
2015 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced,
2017 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced,
2020 // VST3 : Vector Store (multiple 3-element structures)
2031 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
2032 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
2050 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
2051 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
2057 // ...with double-spaced registers:
2059 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
2060 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
2062 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
2063 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
2078 // VST4 : Vector Store (multiple 4-element structures)
2085 let Inst{5-4} = Rn{5-4};
2090 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
2091 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
2104 let Inst{5-4} = Rn{5-4};
2109 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
2110 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
2116 // ...with double-spaced registers:
2118 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
2119 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
2121 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
2122 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
2137 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2139 // Classes for VST*LN pseudo-instructions with multi-register operands.
2142 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2147 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2149 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
2154 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2156 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
2161 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2163 // VST1LN : Vector Store (single element from one lane)
2166 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2167 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2168 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2169 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]>,
2176 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2182 let Inst{7-5} = lane{2-0};
2186 let Inst{7-6} = lane{1-0};
2192 let Inst{7} = lane{0};
2193 let Inst{5-4} = Rn{5-4};
2201 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2202 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2203 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2204 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2206 def : Pat<(store (extractelt (v4f16 DPR:$src), imm:$lane), addrmode6:$addr),
2207 (VST1LNd16 addrmode6:$addr, DPR:$src, imm:$lane)>;
2208 def : Pat<(store (extractelt (v8f16 QPR:$src), imm:$lane), addrmode6:$addr),
2209 (VST1LNq16Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2215 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2217 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2218 "\\{$Vd[$lane]\\}, $Rn$Rm",
2220 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2227 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2233 let Inst{7-5} = lane{2-0};
2237 let Inst{7-6} = lane{1-0};
2242 let Inst{7} = lane{0};
2243 let Inst{5-4} = Rn{5-4};
2250 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2252 // VST2LN : Vector Store (single 2-element structure from one lane)
2254 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2255 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2256 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2264 let Inst{7-5} = lane{2-0};
2267 let Inst{7-6} = lane{1-0};
2270 let Inst{7} = lane{0};
2277 // ...with double-spaced registers:
2278 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2279 let Inst{7-6} = lane{1-0};
2282 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2283 let Inst{7} = lane{0};
2292 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2294 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2295 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2302 let Inst{7-5} = lane{2-0};
2305 let Inst{7-6} = lane{1-0};
2308 let Inst{7} = lane{0};
2315 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2316 let Inst{7-6} = lane{1-0};
2318 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2319 let Inst{7} = lane{0};
2325 // VST3LN : Vector Store (single 3-element structure from one lane)
2327 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2329 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2330 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []>,
2337 let Inst{7-5} = lane{2-0};
2340 let Inst{7-6} = lane{1-0};
2343 let Inst{7} = lane{0};
2350 // ...with double-spaced registers:
2351 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2352 let Inst{7-6} = lane{1-0};
2354 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2355 let Inst{7} = lane{0};
2363 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2365 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2367 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2373 let Inst{7-5} = lane{2-0};
2376 let Inst{7-6} = lane{1-0};
2379 let Inst{7} = lane{0};
2386 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2387 let Inst{7-6} = lane{1-0};
2389 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2390 let Inst{7} = lane{0};
2396 // VST4LN : Vector Store (single 4-element structure from one lane)
2398 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2400 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2401 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2409 let Inst{7-5} = lane{2-0};
2412 let Inst{7-6} = lane{1-0};
2415 let Inst{7} = lane{0};
2423 // ...with double-spaced registers:
2424 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2425 let Inst{7-6} = lane{1-0};
2427 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2428 let Inst{7} = lane{0};
2437 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2439 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2441 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2448 let Inst{7-5} = lane{2-0};
2451 let Inst{7-6} = lane{1-0};
2454 let Inst{7} = lane{0};
2462 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2463 let Inst{7-6} = lane{1-0};
2465 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2466 let Inst{7} = lane{0};
2473 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2516 //===----------------------------------------------------------------------===//
2518 //===----------------------------------------------------------------------===//
2520 // Basic 2-register operations: double- and quad-register.
2530 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2534 // Basic 2-register intrinsics, both double- and quad-register.
2546 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2561 : N2Vnp<op19_18, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2584 // Narrow 2-register operations.
2593 // Narrow 2-register intrinsics.
2602 // Long 2-register operations (currently only used for VMOVL).
2611 // Long 2-register intrinsics.
2620 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2628 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2632 // Basic 3-register operations: double- and quad-register.
2640 // All of these have a two-operand InstAlias.
2653 // All of these have a two-operand InstAlias.
2661 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2662 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2663 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2666 (Ty (ARMvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2667 // All of these have a two-operand InstAlias.
2673 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2674 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2675 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2678 (Ty (ARMvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2679 // All of these have a two-operand InstAlias.
2687 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2691 // All of these have a two-operand InstAlias.
2698 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2702 // All of these have a two-operand InstAlias.
2709 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2710 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2711 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2715 imm:$lane)))))]> {
2716 // All of these have a two-operand InstAlias.
2722 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2723 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2724 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2728 imm:$lane)))))]> {
2729 // All of these have a two-operand InstAlias.
2734 // Basic 3-register intrinsics, both double- and quad-register.
2742 // All of these have a two-operand InstAlias.
2760 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2761 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2762 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2766 imm:$lane)))))]> {
2772 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2773 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2774 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2777 (Ty (ARMvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2794 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2798 // All of these have a two-operand InstAlias.
2830 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2831 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2832 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2836 imm:$lane)))))]> {
2842 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2843 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2844 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2848 imm:$lane)))))]> {
2854 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2862 // Multiply-Add/Sub operations: double- and quad-register.
2875 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2877 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2879 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2884 imm:$lane)))))))]>;
2888 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2890 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2892 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2897 imm:$lane)))))))]>;
2902 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2910 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2912 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2914 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2919 imm:$lane)))))))]>;
2924 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2926 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2928 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2933 imm:$lane)))))))]>;
2935 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2947 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2953 // Neon 3-argument intrinsics, both double- and quad-register.
2966 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2972 // Long Multiply-Add/Sub operations.
2985 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2986 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2988 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2993 imm:$lane))))))]>;
2997 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2998 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3000 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
3005 imm:$lane))))))]>;
3007 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
3019 // Neon Long 3-argument intrinsic. The destination register is
3020 // a quad-register and is also used as the first source operand register.
3032 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
3034 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3036 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
3041 imm:$lane)))))]>;
3045 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
3047 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3049 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
3054 imm:$lane)))))]>;
3056 // Narrowing 3-register intrinsics.
3067 // Long 3-register operations.
3081 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
3082 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3083 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3086 (TyD (ARMvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
3090 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
3091 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3092 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3095 (TyD (ARMvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
3097 // Long 3-register operations with explicitly extended operands.
3110 // Long 3-register intrinsics with explicit extend (VABDL).
3123 // Long 3-register intrinsics.
3149 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
3150 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3151 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3155 imm:$lane)))))]>;
3159 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
3160 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3161 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3165 imm:$lane)))))]>;
3167 // Wide 3-register operations.
3176 // All of these have a two-operand InstAlias.
3181 // Pairwise long 2-register intrinsics, both double- and quad-register.
3193 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3197 // Pairwise long 2-register accumulate intrinsics,
3198 // both double- and quad-register.
3212 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
3218 // both double- and quad-register.
3230 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3258 // both double- and quad-register.
3271 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3279 // both double- and quad-register.
3291 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3298 // both double- and quad-register.
3309 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3314 //===----------------------------------------------------------------------===//
3316 //===----------------------------------------------------------------------===//
3324 // Neon 2-register vector operations and intrinsics.
3326 // Neon 2-register comparisons.
3331 // 64-bit vector types.
3348 let Inst{10} = 1; // overwrite F = 1
3355 let Inst{10} = 1; // overwrite F = 1
3358 // 128-bit vector types.
3359 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3363 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3367 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3371 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3375 let Inst{10} = 1; // overwrite F = 1
3377 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3382 let Inst{10} = 1; // overwrite F = 1
3386 // Neon 3-register comparisons.
3390 : N3V<op24, op23, op21_20, op11_8, 1, op4,
3394 // All of these have a two-operand InstAlias.
3406 // All of these have a two-operand InstAlias.
3416 // 64-bit vector types.
3427 // 128-bit vector types.
3440 // Neon 2-register vector intrinsics,
3446 // 64-bit vector types.
3454 // 128-bit vector types.
3464 // Neon Narrowing 2-register vector operations,
3481 // Neon Narrowing 2-register vector intrinsics,
3499 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3512 // Neon 3-register vector operations.
3520 // 64-bit vector types.
3531 // 128-bit vector types.
3567 // Neon 3-register vector intrinsics.
3575 // 64-bit vector types.
3583 // 128-bit vector types.
3596 // 64-bit vector types.
3604 // 128-bit vector types.
3688 // Neon Narrowing 3-register vector intrinsics,
3705 // Neon Long 3-register vector operations.
3746 // Neon Long 3-register vector intrinsics.
3798 // Neon Wide 3-register vector intrinsics,
3815 // Neon Multiply-Op vector operations,
3821 // 64-bit vector types.
3829 // 128-bit vector types.
3854 // Neon Intrinsic-Op vector operations,
3860 // 64-bit vector types.
3868 // 128-bit vector types.
3877 // Neon 3-argument intrinsics,
3883 // 64-bit vector types.
3889 // 128-bit vector types.
3903 // 64-bit vector types.
3906 // 128-bit vector types.
3911 // Neon Long Multiply-Op vector operations,
3934 // Neon Long 3-argument intrinsics.
3979 // Neon Pairwise long 2-register intrinsics,
3984 // 64-bit vector types.
3992 // 128-bit vector types.
4002 // Neon Pairwise long 2-register accumulate intrinsics,
4007 // 64-bit vector types.
4015 // 128-bit vector types.
4025 // Neon 2-register vector shift by immediate,
4031 // 64-bit vector types.
4034 let Inst{21-19} = 0b001; // imm6 = 001xxx
4038 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4042 let Inst{21} = 0b1; // imm6 = 1xxxxx
4044 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
4048 // 128-bit vector types.
4051 let Inst{21-19} = 0b001; // imm6 = 001xxx
4055 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4059 let Inst{21} = 0b1; // imm6 = 1xxxxx
4061 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
4068 // 64-bit vector types.
4071 let Inst{21-19} = 0b001; // imm6 = 001xxx
4075 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4079 let Inst{21} = 0b1; // imm6 = 1xxxxx
4081 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
4085 // 128-bit vector types.
4088 let Inst{21-19} = 0b001; // imm6 = 001xxx
4092 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4096 let Inst{21} = 0b1; // imm6 = 1xxxxx
4098 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
4103 // Neon Shift-Accumulate vector operations,
4107 // 64-bit vector types.
4110 let Inst{21-19} = 0b001; // imm6 = 001xxx
4114 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4118 let Inst{21} = 0b1; // imm6 = 1xxxxx
4120 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
4124 // 128-bit vector types.
4127 let Inst{21-19} = 0b001; // imm6 = 001xxx
4131 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4135 let Inst{21} = 0b1; // imm6 = 1xxxxx
4137 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
4142 // Neon Shift-Insert vector operations,
4147 // 64-bit vector types.
4150 let Inst{21-19} = 0b001; // imm6 = 001xxx
4154 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4158 let Inst{21} = 0b1; // imm6 = 1xxxxx
4160 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
4164 // 128-bit vector types.
4167 let Inst{21-19} = 0b001; // imm6 = 001xxx
4171 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4175 let Inst{21} = 0b1; // imm6 = 1xxxxx
4177 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
4183 // 64-bit vector types.
4186 let Inst{21-19} = 0b001; // imm6 = 001xxx
4190 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4194 let Inst{21} = 0b1; // imm6 = 1xxxxx
4196 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
4200 // 128-bit vector types.
4203 let Inst{21-19} = 0b001; // imm6 = 001xxx
4207 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4211 let Inst{21} = 0b1; // imm6 = 1xxxxx
4213 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
4225 let Inst{21-19} = 0b001; // imm6 = 001xxx
4229 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4233 let Inst{21} = 0b1; // imm6 = 1xxxxx
4245 let Inst{21-19} = 0b001; // imm6 = 001xxx
4250 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4255 let Inst{21} = 0b1; // imm6 = 1xxxxx
4259 //===----------------------------------------------------------------------===//
4261 //===----------------------------------------------------------------------===//
4265 // VADD : Vector Add (integer and floating-point)
4267 add, 1>;
4269 v2f32, v2f32, fadd, 1>;
4271 v4f32, v4f32, fadd, 1>;
4273 v4f16, v4f16, fadd, 1>,
4276 v8f16, v8f16, fadd, 1>,
4279 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4280 "vaddl", "s", add, sext, 1>;
4281 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4282 "vaddl", "u", add, zanyext, 1>;
4284 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4285 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zanyext, 0>;
4289 "vhadd", "s", int_arm_neon_vhadds, 1>;
4290 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4292 "vhadd", "u", int_arm_neon_vhaddu, 1>;
4296 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
4297 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4299 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
4301 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4303 "vqadd", "s", saddsat, 1>;
4304 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4306 "vqadd", "u", uaddsat, 1>;
4308 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
4310 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
4311 int_arm_neon_vraddhn, 1>;
4324 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4325 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
4326 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
4327 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
4328 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
4329 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
4330 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
4331 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4332 v2f32, v2f32, fmul, 1>;
4333 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4334 v4f32, v4f32, fmul, 1>;
4335 def VMULhd : N3VD<1, 0, 0b01, 0b1101, 1, IIC_VFMULD, "vmul", "f16",
4336 v4f16, v4f16, fmul, 1>,
4338 def VMULhq : N3VQ<1, 0, 0b01, 0b1101, 1, IIC_VFMULQ, "vmul", "f16",
4339 v8f16, v8f16, fmul, 1>,
4353 (v8i16 (ARMvduplane (v8i16 QPR:$src2), imm:$lane)))),
4356 (DSubReg_i16_reg imm:$lane))),
4357 (SubReg_i16_lane imm:$lane)))>;
4359 (v4i32 (ARMvduplane (v4i32 QPR:$src2), imm:$lane)))),
4362 (DSubReg_i32_reg imm:$lane))),
4363 (SubReg_i32_lane imm:$lane)))>;
4365 (v4f32 (ARMvduplane (v4f32 QPR:$src2), imm:$lane)))),
4368 (DSubReg_i32_reg imm:$lane))),
4369 (SubReg_i32_lane imm:$lane)))>;
4371 (v8f16 (ARMvduplane (v8f16 QPR:$src2), imm:$lane)))),
4374 (DSubReg_i16_reg imm:$lane))),
4375 (SubReg_i16_lane imm:$lane)))>;
4398 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4406 imm:$lane)))),
4409 (DSubReg_i16_reg imm:$lane))),
4410 (SubReg_i16_lane imm:$lane)))>;
4413 imm:$lane)))),
4416 (DSubReg_i32_reg imm:$lane))),
4417 (SubReg_i32_lane imm:$lane)))>;
4421 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4423 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4431 imm:$lane)))),
4434 (DSubReg_i16_reg imm:$lane))),
4435 (SubReg_i16_lane imm:$lane)))>;
4438 imm:$lane)))),
4441 (DSubReg_i32_reg imm:$lane))),
4442 (SubReg_i32_lane imm:$lane)))>;
4448 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4449 "vmull", "s", ARMvmulls, 1>;
4450 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4451 "vmull", "u", ARMvmullu, 1>;
4452 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4453 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4455 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4459 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", ARMvmullu>;
4462 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4463 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4467 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4469 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4472 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4475 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4478 def VMLAhd : N3VDMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACD, "vmla", "f16",
4481 def VMLAhq : N3VQMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACQ, "vmla", "f16",
4502 (v8i16 (ARMvduplane (v8i16 QPR:$src3), imm:$lane))))),
4505 (DSubReg_i16_reg imm:$lane))),
4506 (SubReg_i16_lane imm:$lane)))>;
4510 (v4i32 (ARMvduplane (v4i32 QPR:$src3), imm:$lane))))),
4513 (DSubReg_i32_reg imm:$lane))),
4514 (SubReg_i32_lane imm:$lane)))>;
4519 (v4f32 (ARMvduplane (v4f32 QPR:$src3), imm:$lane))))),
4523 (DSubReg_i32_reg imm:$lane))),
4524 (SubReg_i32_lane imm:$lane)))>,
4528 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4530 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4534 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", ARMvmullu, add>;
4537 // v8.1a Neon Rounding Double Multiply-Op vector operations,
4540 defm VQRDMLAH : N3VInt3_HS<1, 0, 0b1011, 1, IIC_VMACi16D, IIC_VMACi32D,
4562 imm:$lane)))),
4564 imm:$lane))>;
4568 imm:$lane)))),
4570 imm:$lane))>;
4574 imm:$lane)))),
4579 (DSubReg_i16_reg imm:$lane))),
4580 (SubReg_i16_lane imm:$lane)))>;
4584 imm:$lane)))),
4589 (DSubReg_i32_reg imm:$lane))),
4590 (SubReg_i32_lane imm:$lane)))>;
4593 // (Q -= D * D)
4594 defm VQRDMLSH : N3VInt3_HS<1, 0, 0b1100, 1, IIC_VMACi16D, IIC_VMACi32D,
4616 imm:$lane)))),
4617 (v4i16 (VQRDMLSHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))>;
4621 imm:$lane)))),
4623 imm:$lane))>;
4627 imm:$lane)))),
4632 (DSubReg_i16_reg imm:$lane))),
4633 (SubReg_i16_lane imm:$lane)))>;
4637 imm:$lane)))),
4642 (DSubReg_i32_reg imm:$lane))),
4643 (SubReg_i32_lane imm:$lane)))>;
4646 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4662 imm:$lane)))))),
4663 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4667 imm:$lane)))))),
4668 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4671 // VMLS : Vector Multiply Subtract (integer and floating-point)
4672 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4674 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4677 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4680 def VMLShd : N3VDMulOp<0, 0, 0b11, 0b1101, 1, IIC_VMACD, "vmls", "f16",
4683 def VMLShq : N3VQMulOp<0, 0, 0b11, 0b1101, 1, IIC_VMACQ, "vmls", "f16",
4704 (v8i16 (ARMvduplane (v8i16 QPR:$src3), imm:$lane))))),
4707 (DSubReg_i16_reg imm:$lane))),
4708 (SubReg_i16_lane imm:$lane)))>;
4712 (v4i32 (ARMvduplane (v4i32 QPR:$src3), imm:$lane))))),
4715 (DSubReg_i32_reg imm:$lane))),
4716 (SubReg_i32_lane imm:$lane)))>;
4721 (v4f32 (ARMvduplane (v4f32 QPR:$src3), imm:$lane))))),
4724 (DSubReg_i32_reg imm:$lane))),
4725 (SubReg_i32_lane imm:$lane)))>,
4728 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4729 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4731 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4735 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", ARMvmullu, sub>;
4737 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4738 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4754 imm:$lane)))))),
4755 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4759 imm:$lane)))))),
4760 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4763 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4764 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4768 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4771 def VFMAhd : N3VDMulOp<0, 0, 0b01, 0b1100, 1, IIC_VFMACD, "vfma", "f16",
4775 def VFMAhq : N3VQMulOp<0, 0, 0b01, 0b1100, 1, IIC_VFMACQ, "vfma", "f16",
4779 // Fused Vector Multiply Subtract (floating-point)
4780 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4783 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4786 def VFMShd : N3VDMulOp<0, 0, 0b11, 0b1100, 1, IIC_VFMACD, "vfms", "f16",
4789 def VFMShq : N3VQMulOp<0, 0, 0b11, 0b1100, 1, IIC_VFMACQ, "vfms", "f16",
4832 def VUDOTD : VDOT<0, 1, 0, DPR, "vudot", "u8", v2i32, v8i8, int_arm_neon_udot>;
4834 def VUDOTQ : VDOT<1, 1, 0, QPR, "vudot", "u8", v4i32, v16i8, int_arm_neon_udot>;
4835 def VSDOTQ : VDOT<1, 0, 0, QPR, "vsdot", "s8", v4i32, v16i8, int_arm_neon_sdot>;
4842 (ins Ty:$Vd, Ty:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
4844 bit lane;
4845 let Inst{5} = lane;
4846 let AsmString = !strconcat(opc, ".", dt, "\t$Vd, $Vn, $Vm$lane");
4857 VectorIndex32:$lane)))))),
4858 (!cast<Instruction>(NAME) Ty:$Vd, Ty:$Vn, RHS, VectorIndex32:$lane)>;
4874 : N3Vnp<{0b1100, B}, 0b10, 0b1100, 1, U, (outs QPR:$dst),
4889 (ins RegTy:$Vd, RegTy:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm,
4891 bit lane;
4892 let Inst{5} = lane;
4893 let AsmString = !strconcat(Asm, ".", AsmTy, "\t$Vd, $Vn, $Vm$lane");
4903 VectorIndex32:$lane)))))),
4904 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4909 : N3VMixedDotLane<Q, 1, "vsudot", "u8", RegTy, AccumTy, InputTy, null_frag, null_frag> {
4914 VectorIndex32:$lane)))),
4916 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4920 def VUMMLA : N3VMatMul<0, 1, "vummla", "u8", int_arm_neon_ummla>;
4921 def VUSMMLA : N3VMatMul<1, 0, "vusmmla", "s8", int_arm_neon_usmmla>;
4922 def VUSDOTD : VDOT<0, 0, 1, DPR, "vusdot", "s8", v2i32, v8i8, int_arm_neon_usdot>;
4923 def VUSDOTQ : VDOT<1, 0, 1, QPR, "vusdot", "s8", v4i32, v16i8, int_arm_neon_usdot>;
4927 defm VUSDOTQI : N3VMixedDotLane<1, 0, "vusdot", "s8", QPR, v4i32, v16i8,
4930 defm VSUDOTQI : SUDOTLane<1, QPR, v4i32, v16i8, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>;
4940 let Inst{24-23} = rot;
4948 bits<1> rot;
4956 "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
4958 bit lane;
4960 let Inst{21-20} = rot;
4961 let Inst{5} = lane;
4968 "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
4970 bit lane;
4972 let Inst{21-20} = rot;
4974 // This is needed because the lane operand does not have any bits in the
4986 def v8f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 1, IIC_VMACQ, (outs QPR:$Vd),
4991 def v2f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 0, IIC_VMACD, (outs DPR:$Vd),
4994 def v4f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 1, IIC_VMACQ, (outs QPR:$Vd),
5007 def v8f16 : BaseN3VCP8ComplexOdd<op23, op21, op4, 0, 1, IIC_VMACQ,
5013 def v2f32 : BaseN3VCP8ComplexOdd<op23, op21, op4, 1, 0, IIC_VMACD,
5017 def v4f32 : BaseN3VCP8ComplexOdd<op23, op21, op4, 1, 1, IIC_VMACQ,
5031 VectorIndex32:$lane, complexrotateop:$rot),
5033 def v8f16_indexed : BaseN3VCP8ComplexTiedLane32<op4, 0, 1, IIC_VMACQ,
5036 VectorIndex32:$lane, complexrotateop:$rot),
5040 def v2f32_indexed : BaseN3VCP8ComplexTiedLane64<op4, 1, 0, IIC_VMACD,
5042 (ins DPR:$src1, DPR:$Vn, DPR:$Vm, VectorIndex64:$lane,
5045 def v4f32_indexed : BaseN3VCP8ComplexTiedLane64<op4, 1, 1, IIC_VMACQ,
5047 (ins QPR:$src1, QPR:$Vn, DPR:$Vm, VectorIndex64:$lane,
5053 defm VCMLA : N3VCP8ComplexTied<1, 0, "vcmla">;
5054 defm VCADD : N3VCP8ComplexOdd<1, 0, 0, "vcadd">;
5061 (VCADDv4f16 (v4f16 DPR:$Rn), (v4f16 DPR:$Rm), (i32 1))>;
5065 (VCADDv8f16 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm), (i32 1))>;
5071 (VCADDv2f32 (v2f32 DPR:$Rn), (v2f32 DPR:$Rm), (i32 1))>;
5075 (VCADDv4f32 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm), (i32 1))>;
5080 // VSUB : Vector Subtract (integer and floating-point)
5081 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
5093 // VSUBL : Vector Subtract Long (Q = D - D)
5094 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
5096 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
5098 // VSUBW : Vector Subtract Wide (Q = Q - D)
5099 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
5100 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zanyext, 0>;
5105 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
5109 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
5112 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
5115 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
5116 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
5117 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
5118 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
5133 defm VCEQ : N3V_QHS_cmp<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5134 IIC_VSUBi4Q, "vceq", "i", ARMCCeq, 1>;
5136 ARMCCeq, 1>;
5138 ARMCCeq, 1>;
5140 ARMCCeq, 1>,
5143 ARMCCeq, 1>,
5151 defm VCGEs : N3V_QHS_cmp<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5153 defm VCGEu : N3V_QHS_cmp<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5155 def VCGEfd : N3VD_cmp<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
5157 def VCGEfq : N3VQ_cmp<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
5159 def VCGEhd : N3VD_cmp<1,0,0b01,0b1110,0, IIC_VBIND, "vcge", "f16", v4i16, v4f16,
5162 def VCGEhq : N3VQ_cmp<1,0,0b01,0b1110,0, IIC_VBINQ, "vcge", "f16", v8i16, v8f16,
5176 defm VCGTu : N3V_QHS_cmp<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5178 def VCGTfd : N3VD_cmp<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
5180 def VCGTfq : N3VQ_cmp<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
5182 def VCGThd : N3VD_cmp<1,0,0b11,0b1110,0, IIC_VBIND, "vcgt", "f16", v4i16, v4f16,
5185 def VCGThq : N3VQ_cmp<1,0,0b11,0b1110,0, IIC_VBINQ, "vcgt", "f16", v8i16, v8f16,
5197 def VACGEfd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
5199 def VACGEfq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
5201 def VACGEhd : N3VDInt<1, 0, 0b01, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
5204 def VACGEhq : N3VQInt<1, 0, 0b01, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
5208 def VACGTfd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
5210 def VACGTfq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
5212 def VACGThd : N3VDInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
5215 def VACGThq : N3VQInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
5219 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
5220 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
5246 : N3VCP8<op1, op2, 1, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
5254 // Vd, Vs, Vs[0-15], Idx[0-1]
5256 : N3VLaneCP8<0, S, 0, 1, (outs DPR:$Vd),
5261 let Inst{19-16} = Vn{4-1};
5264 let Inst{2-0} = Vm{3-1};
5267 // Vq, Vd, Vd[0-7], Idx[0-3]
5269 : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd),
5273 let Inst{5} = idx{1};
5278 def VFMALD : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>;
5279 def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
5280 def VFMALQ : N3VCP8F16Q1<"vfmal", QPR, DPR, DPR, 0b00, 0b10, 1>;
5281 def VFMSLQ : N3VCP8F16Q1<"vfmsl", QPR, DPR, DPR, 0b01, 0b10, 1>;
5317 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
5318 v2i32, v2i32, and, 1>;
5319 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
5320 v4i32, v4i32, and, 1>;
5323 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
5324 v2i32, v2i32, xor, 1>;
5325 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
5326 v4i32, v4i32, xor, 1>;
5329 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
5330 v2i32, v2i32, or, 1>;
5331 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
5332 v4i32, v4i32, or, 1>;
5357 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
5366 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
5372 let Inst{10-9} = SIMM{10-9};
5375 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
5384 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
5390 let Inst{10-9} = SIMM{10-9};
5396 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5401 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5413 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
5422 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
5428 let Inst{10-9} = SIMM{10-9};
5431 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
5440 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
5446 let Inst{10-9} = SIMM{10-9};
5450 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
5455 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
5468 let isReMaterializable = 1 in {
5470 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
5477 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
5484 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
5488 let Inst{11-8} = SIMM{11-8};
5491 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
5495 let Inst{11-8} = SIMM{11-8};
5504 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
5600 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5606 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5614 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
5619 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
5627 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
5632 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
5643 "vabd", "s", abds, 1>;
5644 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
5646 "vabd", "u", abdu, 1>;
5647 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
5648 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
5649 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
5650 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
5651 def VABDhd : N3VDInt<1, 0, 0b11, 0b1101, 0, N3RegFrm, IIC_VBIND,
5652 "vabd", "f16", v4f16, v4f16, int_arm_neon_vabds, 1>,
5654 def VABDhq : N3VQInt<1, 0, 0b11, 0b1101, 0, N3RegFrm, IIC_VBINQ,
5655 "vabd", "f16", v8f16, v8f16, int_arm_neon_vabds, 1>,
5658 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
5659 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
5660 "vabdl", "s", abds, zext, 1>;
5661 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
5662 "vabdl", "u", abdu, zext, 1>;
5674 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
5676 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
5679 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
5680 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
5682 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
5690 "vmax", "s", smax, 1>;
5691 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
5693 "vmax", "u", umax, 1>;
5696 v2f32, v2f32, fmaximum, 1>;
5699 v4f32, v4f32, fmaximum, 1>;
5702 v4f16, v4f16, fmaximum, 1>,
5706 v8f16, v8f16, fmaximum, 1>,
5711 def NEON_VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
5713 v2f32, v2f32, fmaxnum, 1>,
5715 def NEON_VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
5717 v4f32, v4f32, fmaxnum, 1>,
5719 def NEON_VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1,
5721 v4f16, v4f16, fmaxnum, 1>,
5723 def NEON_VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1,
5725 v8f16, v8f16, fmaxnum, 1>,
5730 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
5732 "vmin", "s", smin, 1>;
5733 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
5735 "vmin", "u", umin, 1>;
5738 v2f32, v2f32, fminimum, 1>;
5741 v4f32, v4f32, fminimum, 1>;
5744 v4f16, v4f16, fminimum, 1>,
5748 v8f16, v8f16, fminimum, 1>,
5753 def NEON_VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
5755 v2f32, v2f32, fminnum, 1>,
5757 def NEON_VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
5759 v4f32, v4f32, fminnum, 1>,
5761 def NEON_VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1,
5763 v4f16, v4f16, fminnum, 1>,
5765 def NEON_VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1,
5767 v8f16, v8f16, fminnum, 1>,
5774 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5777 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5780 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5783 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
5786 def VPADDh : N3VDInt<1, 0, 0b01, 0b1101, 0, N3RegFrm,
5810 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5812 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5814 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5816 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
5818 def VPMAXh : N3VDInt<1, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
5823 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5825 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5827 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5829 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5831 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5833 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5835 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
5837 def VPMINh : N3VDInt<1, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
5866 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
5868 v2f32, v2f32, int_arm_neon_vrecps, 1>;
5869 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
5871 v4f32, v4f32, int_arm_neon_vrecps, 1>;
5872 def VRECPShd : N3VDInt<0, 0, 0b01, 0b1111, 1, N3RegFrm,
5874 v4f16, v4f16, int_arm_neon_vrecps, 1>,
5876 def VRECPShq : N3VQInt<0, 0, 0b01, 0b1111, 1, N3RegFrm,
5878 v8f16, v8f16, int_arm_neon_vrecps, 1>,
5904 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
5906 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
5907 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
5909 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
5910 def VRSQRTShd : N3VDInt<0, 0, 0b11, 0b1111, 1, N3RegFrm,
5912 v4f16, v4f16, int_arm_neon_vrsqrts, 1>,
5914 def VRSQRTShq : N3VQInt<0, 0, 0b11, 0b1111, 1, N3RegFrm,
5916 v8f16, v8f16, int_arm_neon_vrsqrts, 1>,
5925 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
5967 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", ARMvshlImm>;
5970 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",
5972 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",
5976 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s",
5978 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u",
5987 let Inst{21-16} = op21_16;
5990 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
5992 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
5994 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
6019 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
6036 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
6040 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",
6042 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",
6046 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
6050 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
6053 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
6057 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshlsImm>;
6058 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshluImm>;
6061 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsuImm>;
6064 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
6066 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
6070 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
6074 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
6077 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
6082 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
6084 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
6088 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
6092 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", ARMvshrsImm>;
6093 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", ARMvshruImm>;
6095 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrsImm>;
6096 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshruImm>;
6099 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
6102 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
6141 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
6153 // VNEG : Vector Negate (floating-point)
6158 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
6167 def VNEGhq : N2V<0b11, 0b11, 0b01, 0b01, 0b01111, 1, 0,
6210 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
6228 let isReMaterializable = 1, isAsCheapAsAMove=1 in {
6229 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
6233 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
6238 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
6245 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
6252 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
6256 let Inst{11-8} = SIMM{11-8};
6259 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
6263 let Inst{11-8} = SIMM{11-8};
6266 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
6270 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
6275 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
6279 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
6313 // "vmov.i32 d0, #0xab00ab00" -> "vmov.i16 d0, #0xab00"
6314 // "vmvn.i64 q0, #0xab000000ab000000" -> "vmvn.i32 q0, #0xab000000"
6334 // TODO: add "VMOV <-> VMVN" conversion for cases like
6335 // "vmov.i32 d0, #0xffaaffaa" -> "vmvn.i16 d0, #0x55"
6336 // "vmvn.i32 d0, #0xaaffaaff" -> "vmov.i16 d0, #0xff00"
6342 // Even without these pseudo-insts we would probably end up with the correct
6346 let AddedComplexity = 50, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
6357 // VMOV : Vector Get Lane (move scalar to ARM core register)
6359 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
6360 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
6361 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
6363 imm:$lane))]> {
6364 let Inst{21} = lane{2};
6365 let Inst{6-5} = lane{1-0};
6367 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
6368 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
6369 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
6371 imm:$lane))]> {
6372 let Inst{21} = lane{1};
6373 let Inst{6} = lane{0};
6375 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
6376 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
6377 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
6379 imm:$lane))]> {
6380 let Inst{21} = lane{2};
6381 let Inst{6-5} = lane{1-0};
6383 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
6384 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
6385 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
6387 imm:$lane))]> {
6388 let Inst{21} = lane{1};
6389 let Inst{6} = lane{0};
6391 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
6392 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
6393 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
6395 imm:$lane))]>,
6397 let Inst{21} = lane{0};
6400 def : InstAlias<"vmov${p} $R, $V$lane",
6401 (VGETLNi32 GPR:$R, DPR:$V, VectorIndex32:$lane, pred:$p), 0>,
6405 def : Pat<(ARMvgetlanes (v16i8 QPR:$src), imm:$lane),
6407 (DSubReg_i8_reg imm:$lane))),
6408 (SubReg_i8_lane imm:$lane))>;
6409 def : Pat<(ARMvgetlanes (v8i16 QPR:$src), imm:$lane),
6411 (DSubReg_i16_reg imm:$lane))),
6412 (SubReg_i16_lane imm:$lane))>;
6413 def : Pat<(ARMvgetlaneu (v16i8 QPR:$src), imm:$lane),
6415 (DSubReg_i8_reg imm:$lane))),
6416 (SubReg_i8_lane imm:$lane))>;
6417 def : Pat<(ARMvgetlaneu (v8i16 QPR:$src), imm:$lane),
6419 (DSubReg_i16_reg imm:$lane))),
6420 (SubReg_i16_lane imm:$lane))>;
6421 def : Pat<(ARMvgetlaneu (v8f16 QPR:$src), imm:$lane),
6423 (DSubReg_i16_reg imm:$lane))),
6424 (SubReg_i16_lane imm:$lane))>;
6425 def : Pat<(ARMvgetlaneu (v4f16 DPR:$src), imm:$lane),
6426 (VGETLNu16 (v4f16 DPR:$src), imm:$lane)>;
6427 def : Pat<(ARMvgetlaneu (v8bf16 QPR:$src), imm:$lane),
6429 (DSubReg_i16_reg imm:$lane))),
6430 (SubReg_i16_lane imm:$lane))>;
6431 def : Pat<(ARMvgetlaneu (v4bf16 DPR:$src), imm:$lane),
6432 (VGETLNu16 (v4bf16 DPR:$src), imm:$lane)>;
6434 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
6436 (DSubReg_i32_reg imm:$lane))),
6437 (SubReg_i32_lane imm:$lane))>,
6439 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
6441 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
6443 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
6445 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
6461 def : Pat<(extractelt (VT4 DPR:$src), imm_even:$lane),
6464 (SSubReg_f16_reg imm_even:$lane))>;
6465 def : Pat<(extractelt (VT8 QPR:$src), imm_even:$lane),
6468 (SSubReg_f16_reg imm_even:$lane))>;
6472 def : Pat<(extractelt (VT4 DPR:$src), imm_odd:$lane),
6476 (SSubReg_f16_reg imm_odd:$lane))),
6478 def : Pat<(extractelt (VT8 QPR:$src), imm_odd:$lane),
6482 (SSubReg_f16_reg imm_odd:$lane))),
6491 let AddedComplexity = 1, Predicates = [HasNEON, HasBF16, HasFullFP16] in {
6499 // Otherwise, if VMOVH is not available resort to extracting the odd lane
6501 def : Pat<(extractelt (v4bf16 DPR:$src), imm_odd:$lane),
6503 (VGETLNu16 (v4bf16 DPR:$src), imm:$lane),
6506 def : Pat<(extractelt (v8bf16 QPR:$src), imm_odd:$lane),
6509 (DSubReg_i16_reg imm:$lane))),
6510 (SubReg_i16_lane imm:$lane)),
6514 // VMOV : Vector Set Lane (move ARM core register to scalar)
6517 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
6518 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
6519 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
6521 GPR:$R, imm:$lane))]> {
6522 let Inst{21} = lane{2};
6523 let Inst{6-5} = lane{1-0};
6525 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
6526 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
6527 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
6529 GPR:$R, imm:$lane))]> {
6530 let Inst{21} = lane{1};
6531 let Inst{6} = lane{0};
6533 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
6534 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
6535 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
6537 GPR:$R, imm:$lane))]>,
6539 let Inst{21} = lane{0};
6542 let isInsertSubreg = 1;
6546 def : InstAlias<"vmov${p} $V$lane, $R",
6547 (VSETLNi32 DPR:$V, GPR:$R, VectorIndex32:$lane, pred:$p), 0>,
6553 def : Pat<(insertelt (VT4 DPR:$src1), (VTScalar HPR:$src2), imm:$lane),
6555 (COPY_TO_REGCLASS HPR:$src2, GPR), imm:$lane))>;
6556 def : Pat<(insertelt (VT8 QPR:$src1), (VTScalar HPR:$src2), imm:$lane),
6559 (DSubReg_i16_reg imm:$lane))),
6561 (SubReg_i16_lane imm:$lane))),
6562 (DSubReg_i16_reg imm:$lane)))>;
6566 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
6569 (DSubReg_i8_reg imm:$lane))),
6570 GPR:$src2, (SubReg_i8_lane imm:$lane))),
6571 (DSubReg_i8_reg imm:$lane)))>;
6572 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
6575 (DSubReg_i16_reg imm:$lane))),
6576 GPR:$src2, (SubReg_i16_lane imm:$lane))),
6577 (DSubReg_i16_reg imm:$lane)))>;
6578 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
6581 (DSubReg_i32_reg imm:$lane))),
6582 GPR:$src2, (SubReg_i32_lane imm:$lane))),
6583 (DSubReg_i32_reg imm:$lane)))>;
6658 // ARMvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
6664 // VDUP : Vector Duplicate Lane (from scalar to all elements)
6668 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6669 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
6670 [(set DPR:$Vd, (Ty (ARMvduplane (Ty DPR:$Vm), imm:$lane)))]>;
6674 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6675 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
6677 VectorIndex32:$lane)))]>;
6679 // Inst{19-16} is partially specified depending on the element size.
6681 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
6682 bits<3> lane;
6683 let Inst{19-17} = lane{2-0};
6685 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
6686 bits<2> lane;
6687 let Inst{19-18} = lane{1-0};
6689 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
6690 bits<1> lane;
6691 let Inst{19} = lane{0};
6693 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
6694 bits<3> lane;
6695 let Inst{19-17} = lane{2-0};
6697 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
6698 bits<2> lane;
6699 let Inst{19-18} = lane{1-0};
6701 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
6702 bits<1> lane;
6703 let Inst{19} = lane{0};
6707 def : Pat<(v4f16 (ARMvduplane (v4f16 DPR:$Vm), imm:$lane)),
6708 (VDUPLN16d DPR:$Vm, imm:$lane)>;
6710 def : Pat<(v2f32 (ARMvduplane (v2f32 DPR:$Vm), imm:$lane)),
6711 (VDUPLN32d DPR:$Vm, imm:$lane)>;
6713 def : Pat<(v4f32 (ARMvduplane (v2f32 DPR:$Vm), imm:$lane)),
6714 (VDUPLN32q DPR:$Vm, imm:$lane)>;
6716 def : Pat<(v16i8 (ARMvduplane (v16i8 QPR:$src), imm:$lane)),
6718 (DSubReg_i8_reg imm:$lane))),
6719 (SubReg_i8_lane imm:$lane)))>;
6720 def : Pat<(v8i16 (ARMvduplane (v8i16 QPR:$src), imm:$lane)),
6722 (DSubReg_i16_reg imm:$lane))),
6723 (SubReg_i16_lane imm:$lane)))>;
6724 def : Pat<(v8f16 (ARMvduplane (v8f16 QPR:$src), imm:$lane)),
6726 (DSubReg_i16_reg imm:$lane))),
6727 (SubReg_i16_lane imm:$lane)))>;
6728 def : Pat<(v4i32 (ARMvduplane (v4i32 QPR:$src), imm:$lane)),
6730 (DSubReg_i32_reg imm:$lane))),
6731 (SubReg_i32_lane imm:$lane)))>;
6732 def : Pat<(v4f32 (ARMvduplane (v4f32 QPR:$src), imm:$lane)),
6734 (DSubReg_i32_reg imm:$lane))),
6735 (SubReg_i32_lane imm:$lane)))>;
6752 def : Pat<(v4bf16 (ARMvduplane (v4bf16 DPR:$Vm), imm:$lane)),
6753 (VDUPLN16d DPR:$Vm, imm:$lane)>;
6755 def : Pat<(v8bf16 (ARMvduplane (v8bf16 QPR:$src), imm:$lane)),
6757 (DSubReg_i16_reg imm:$lane))),
6758 (SubReg_i16_lane imm:$lane)))>;
6774 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
6776 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
6779 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
6780 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
6790 // VCVT : Vector Convert Between Floating-Point and Integers
6843 def UDf : N2VDIntnp<0b10, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
6845 def UQf : N2VQIntnp<0b10, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
6853 def UDh : N2VDIntnp<0b01, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
6856 def UQh : N2VQIntnp<0b01, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
6867 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
6869 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
6871 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
6873 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
6875 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
6878 def VCVTh2xsd : N2VCvtD<0, 1, 0b1101, 0, 1, "vcvt", "s16.f16",
6880 def VCVTh2xud : N2VCvtD<1, 1, 0b1101, 0, 1, "vcvt", "u16.f16",
6882 def VCVTxs2hd : N2VCvtD<0, 1, 0b1100, 0, 1, "vcvt", "f16.s16",
6884 def VCVTxu2hd : N2VCvtD<1, 1, 0b1100, 0, 1, "vcvt", "f16.u16",
6890 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
6892 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
6894 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
6896 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
6899 def VCVTh2xsq : N2VCvtQ<0, 1, 0b1101, 0, 1, "vcvt", "s16.f16",
6901 def VCVTh2xuq : N2VCvtQ<1, 1, 0b1101, 0, 1, "vcvt", "u16.f16",
6903 def VCVTxs2hq : N2VCvtQ<0, 1, 0b1100, 0, 1, "vcvt", "f16.s16",
6905 def VCVTxu2hq : N2VCvtQ<1, 1, 0b1100, 0, 1, "vcvt", "f16.u16",
6947 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
6962 // VREV64 : Vector Reverse elements within 64-bit doublewords
6970 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
6999 // VREV32 : Vector Reverse elements within 32-bit words
7007 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
7029 // VREV16 : Vector Reverse elements within 16-bit halfwords
7037 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
7065 // All of these have a two-operand InstAlias.
7068 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
7075 let Inst{10-8} = index{2-0};
7079 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
7085 let Inst{11-8} = index{3-0};
7090 let Inst{10-8} = index{2-0};
7093 let Inst{10-9} = index{1-0};
7105 let Inst{9-8} = 0b00;
7113 let Inst{11-8} = index{3-0};
7116 let Inst{11-9} = index{2-0};
7127 let Inst{11-10} = index{1-0};
7128 let Inst{9-8} = 0b00;
7132 let Inst{10-8} = 0b000;
7153 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
7165 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
7178 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
7183 let hasExtraSrcRegAllocReq = 1 in {
7185 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
7189 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
7193 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
7197 } // hasExtraSrcRegAllocReq = 1
7206 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
7211 let hasExtraSrcRegAllocReq = 1 in {
7213 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
7217 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
7223 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
7227 } // hasExtraSrcRegAllocReq = 1
7288 let Inst{9-7} = op9_7;
7293 let Inst{9-7} = op9_7;
7299 let Inst{9-7} = op9_7;
7305 let Inst{9-7} = op9_7;
7346 : N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
7351 let isCommutable = 1 in {
7352 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
7355 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
7356 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
7360 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>;
7361 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
7362 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
7363 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, null_frag>;
7364 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, null_frag>;
7365 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>;
7366 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
7402 //===----------------------------------------------------------------------===//
7403 // NEON instructions for single-precision FP math
7404 //===----------------------------------------------------------------------===//
7489 def : VFPPat<(f64 (sint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
7490 (VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
7491 def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
7492 (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
7493 def : VFPPat<(f64 (uint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
7494 (VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
7495 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
7496 (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
7499 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
7507 //===----------------------------------------------------------------------===//
7508 // Non-Instruction Patterns or Endianess - Revert Patterns
7509 //===----------------------------------------------------------------------===//
7780 // Use VLD1/VST1 + VREV for non-word-aligned v2f64 load/store on Big Endian
7793 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
7794 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>,
7956 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
8027 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
8028 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
8029 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
8032 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
8033 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
8035 // Double lengthening - v4i8 -> v4i16 -> v4i32
8037 // v2i8 -> v2i16 -> v2i32
8039 // v2i16 -> v2i32 -> v2i64
8044 defm : Lengthen_HalfSingle_Big_Endian<"4", "i16", "i8", "8", "i16", "8">; // v4i8 -> v4i16
8045 defm : Lengthen_HalfSingle_Big_Endian<"2", "i32", "i16", "4", "i32", "16">; // v2i16 -> v2i32
8047 // Double lengthening - v4i8 -> v4i16 -> v4i32
8049 // v2i8 -> v2i16 -> v2i32
8051 // v2i16 -> v2i32 -> v2i64
8055 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
8108 //===----------------------------------------------------------------------===//
8113 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
8134 // ... two-operand aliases
8158 // VLD1 single-lane pseudo-instructions. These need special handling for
8159 // the lane index that an InstAlias can't handle, so we use these instead.
8196 // VST1 single-lane pseudo-instructions. These need special handling for
8197 // the lane index that an InstAlias can't handle, so we use these instead.
8233 // VLD2 single-lane pseudo-instructions. These need special handling for
8234 // the lane index that an InstAlias can't handle, so we use these instead.
8292 // VST2 single-lane pseudo-instructions. These need special handling for
8293 // the lane index that an InstAlias can't handle, so we use these instead.
8351 // VLD3 all-lanes pseudo-instructions. These need special handling for
8352 // the lane index that an InstAlias can't handle, so we use these instead.
8422 // VLD3 single-lane pseudo-instructions. These need special handling for
8423 // the lane index that an InstAlias can't handle, so we use these instead.
8481 // VLD3 multiple structure pseudo-instructions. These need special handling for
8540 // VST3 single-lane pseudo-instructions. These need special handling for
8541 // the lane index that an InstAlias can't handle, so we use these instead.
8600 // VST3 multiple structure pseudo-instructions. These need special handling for
8659 // VLD4 all-lanes pseudo-instructions. These need special handling for
8660 // the lane index that an InstAlias can't handle, so we use these instead.
8730 // VLD4 single-lane pseudo-instructions. These need special handling for
8731 // the lane index that an InstAlias can't handle, so we use these instead.
8791 // VLD4 multiple structure pseudo-instructions. These need special handling for
8862 // VST4 single-lane pseudo-instructions. These need special handling for
8863 // the lane index that an InstAlias can't handle, so we use these instead.
8922 // VST4 multiple structure pseudo-instructions. These need special handling for
9005 // D-register versions.
9023 // Q-register versions.
9043 // D-register versions.
9061 // Q-register versions.
9100 // "vmov Rd, #-imm" can be handled via "vmvn".
9110 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
9186 DPR_VFP2:$Vm, VectorIndex32:$lane), []> {
9187 bit lane;
9188 let Inst{5} = lane;
9190 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm$lane");
9199 VectorIndex32:$lane)))))),
9200 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
9204 def BF16VDOTS_VDOTQ : BF16VDOTS<1, QPR, "vdot", v4f32, v8bf16>;
9207 defm BF16VDOTI_VDOTQ : BF16VDOTI<1, QPR, "vdot", v4f32, v8bf16, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>;
9222 def VMMLA : BF16MM<1, QPR, "vmmla">;
9225 : N3VCP8<0b00, 0b11, T, 1,
9236 def VBF16MALTQ: VBF16MALQ<1, "t", int_arm_neon_bfmlalt>;
9240 def "" : N3VLaneCP8<0, 0b11, T, 1, (outs QPR:$dst),
9244 let Inst{5} = idx{1};
9254 VectorIndex16:$lane)))),
9258 (DSubReg_i16_reg VectorIndex16:$lane)),
9259 (SubReg_i16_lane VectorIndex16:$lane))>;
9262 defm VBF16MALTQI: VBF16MALQI<1, "t", int_arm_neon_bfmlalt>;
9265 def BF16_VCVT : N2V<0b11, 0b11, 0b01, 0b10, 0b01100, 1, 0,