Lines Matching refs:pred
243 ValueType pred, ValueType dblpred,
257 ValueType Pred = pred;
704 def : Pat<(i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
707 (i32 (InstN $vec, ARMVCCThen, $pred, zero_reg))>;
710 def : Pat<(i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
711 (i32 (InstN $vec, ARMVCCThen, $pred, zero_reg))>;
715 def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
719 (i32 (InstA $acc, $vec, ARMVCCThen, $pred, zero_reg))>;
723 def : Pat<(i32 (add (i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
725 (i32 (InstA $acc, $vec, ARMVCCThen, $pred, zero_reg))>;
732 def : Pat<(i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
733 (i32 (InstN $vec, ARMVCCThen, $pred, zero_reg))>;
734 def : Pat<(i32 (add (i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
736 (i32 (InstA $acc, $vec, ARMVCCThen, $pred, zero_reg))>;
741 (VTI.Pred VCCR:$pred))),
742 (i32 (InstN $vec, ARMVCCThen, $pred, zero_reg))>;
745 (VTI.Pred VCCR:$pred)),
747 (i32 (InstA $acc, $vec, ARMVCCThen, $pred, zero_reg))>;
817 def : Pat<(ARMVADDLVp (v4i32 MQPR:$vec), (VTI.Pred VCCR:$pred)),
818 (InstN (v4i32 MQPR:$vec), ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg)>;
820 (VTI.Pred VCCR:$pred)),
822 ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg)>;
870 (VTI.Pred VCCR:$pred))),
873 ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg),
926 def : Pat<(i32 !con(args, (pred_intr (VTI.Pred VCCR:$pred)))),
928 ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg))>;
1195 def : Pat<(i32 (vecreduce_add (vselect (v4i1 VCCR:$pred),
1198 (i32 (MVE_VMLADAVu32 $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
1199 def : Pat<(i32 (vecreduce_add (vselect (v8i1 VCCR:$pred),
1202 (i32 (MVE_VMLADAVu16 $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
1203 def : Pat<(i32 (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))),
1204 (i32 (MVE_VMLADAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
1205 def : Pat<(i32 (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))),
1206 (i32 (MVE_VMLADAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
1207 def : Pat<(i32 (vecreduce_add (vselect (v16i1 VCCR:$pred),
1210 (i32 (MVE_VMLADAVu8 $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
1211 def : Pat<(i32 (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))),
1212 (i32 (MVE_VMLADAVs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
1213 def : Pat<(i32 (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))),
1214 (i32 (MVE_VMLADAVu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
1216 def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v4i1 VCCR:$pred),
1220 (i32 (MVE_VMLADAVau32 $src3, $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
1221 def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v8i1 VCCR:$pred),
1225 (i32 (MVE_VMLADAVau16 $src3, $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
1226 def : Pat<(i32 (add (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)),
1227 (i32 (MVE_VMLADAVas16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
1228 def : Pat<(i32 (add (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)),
1229 (i32 (MVE_VMLADAVau16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
1230 def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v16i1 VCCR:$pred),
1234 (i32 (MVE_VMLADAVau8 $src3, $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
1235 def : Pat<(i32 (add (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)),
1236 (i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
1237 def : Pat<(i32 (add (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)),
1238 (i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
1361 def : Pat<(ARMVMLALVps (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
1362 (MVE_VMLALDAVs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
1363 def : Pat<(ARMVMLALVpu (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
1364 (MVE_VMLALDAVu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
1365 def : Pat<(ARMVMLALVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
1366 (MVE_VMLALDAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
1367 def : Pat<(ARMVMLALVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
1368 (MVE_VMLALDAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
1370 def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
1371 (MVE_VMLALDAVas32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
1372 def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
1373 (MVE_VMLALDAVau32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
1374 def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
1375 (MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
1376 def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
1377 (MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
1573 revbits, (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive))),
1575 (VTI.Pred VCCR:$pred), zero_reg, (VTI.Vec MQPR:$inactive)))>;
1606 (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive))),
1608 (VTI.Pred VCCR:$pred), zero_reg, (VTI.Vec MQPR:$inactive)))>;
1721 def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
1724 ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg))>;
2413 def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred),
2416 (MVE_VDUP8 rGPR:$elem, ARMVCCThen, (v16i1 VCCR:$pred), zero_reg,
2418 def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred),
2421 (MVE_VDUP16 rGPR:$elem, ARMVCCThen, (v8i1 VCCR:$pred), zero_reg,
2423 def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred),
2426 (MVE_VDUP32 rGPR:$elem, ARMVCCThen, (v4i1 VCCR:$pred), zero_reg,
2428 def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred),
2431 (MVE_VDUP32 rGPR:$elem, ARMVCCThen, (v4i1 VCCR:$pred), zero_reg,
2433 def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred),
2436 (MVE_VDUP16 rGPR:$elem, ARMVCCThen, (v8i1 VCCR:$pred), zero_reg,
2481 def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$val), (VTI.Pred VCCR:$pred),
2484 (VTI.Pred VCCR:$pred), zero_reg, (VTI.Vec MQPR:$inactive)))>;
2651 def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (ARMvmvnImm timm:$simm),
2654 ARMVCCThen, VCCR:$pred, zero_reg, MQPR:$inactive))>;
2655 def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (ARMvmvnImm timm:$simm),
2658 ARMVCCThen, VCCR:$pred, zero_reg, MQPR:$inactive))>;
2777 (OutVTI.Pred VCCR:$pred),
2780 (OutVTI.Pred VCCR:$pred), zero_reg,
3085 (InVTI.Pred VCCR:$pred)))),
3086 (OutVTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred, zero_reg)))>;
3285 def : Pat<(VTI.Vec !con(inparams, (pred_int (VTI.Pred VCCR:$pred)))),
3286 (VTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred, zero_reg)))>;
3588 def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$val), (VTI.Pred VCCR:$pred),
3591 (VTI.Pred VCCR:$pred), zero_reg, (VTI.Vec MQPR:$inactive)))>;
3736 defvar pred = (VTI.Pred VCCR:$pred);
3742 def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
3745 (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
3746 def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)),
3747 (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
3748 def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)),
3749 (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
3753 def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
3756 (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
3757 def : Pat<(VTI.Vec (pred_int m1, m2, add, pred)),
3758 (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
4009 (Flt.Vec MQPR:$in), (Flt.Pred VCCR:$pred))),
4011 (Flt.Pred VCCR:$pred), zero_reg, (Int.Vec MQPR:$inactive)))>;
4578 (? (VTI.Pred VCCR:$pred)))),
4581 ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg))>;
4905 (InVTI.Pred VCCR:$pred))),
4908 ARMVCCThen, (InVTI.Pred VCCR:$pred), zero_reg))>;
4927 (InVTI.Pred VCCR:$pred))),
4930 ARMVCCThen, (InVTI.Pred VCCR:$pred), zero_reg))>;
5641 defvar pred = (VTI.Pred VCCR:$pred);
5652 def : Pat<(VTI.Vec (pred_int v1, v2, s, pred)),
5653 (VTI.Vec (Inst v1, v2, s, ARMVCCThen, pred, zero_reg))>;
5674 defvar pred = (VTI.Pred VCCR:$pred);
5680 def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
5683 (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred, zero_reg))>;
5684 def : Pat<(VTI.Vec (pred_int v1, v2, vs, pred)),
5685 (VTI.Vec (Inst v1, v2, is, ARMVCCThen, pred, zero_reg))>;
5691 def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
5694 (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred, zero_reg))>;
5695 def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
5698 (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred, zero_reg))>;
5699 def : Pat<(VTI.Vec (pred_int v1, vs, v2, pred)),
5700 (VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred, zero_reg))>;
5701 def : Pat<(VTI.Vec (pred_int vs, v1, v2, pred)),
5702 (VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred, zero_reg))>;
5739 (i32 rGPR:$s), (VTI.Pred VCCR:$pred))),
5742 (VTI.Pred VCCR:$pred), zero_reg))>;
6389 def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag, (VTI.Pred VCCR:$pred))),
6390 (VTI.Vec (InstU GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg))>;
6391 def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag, (VTI.Pred VCCR:$pred))),
6392 (VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg))>;
6403 def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned, (VTI.Pred VCCR:$pred))),
6404 (VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg))>;
6418 def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0, (VTI.Pred VCCR:$pred)),
6419 (InstU MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg)>;
6420 def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift, (VTI.Pred VCCR:$pred)),
6421 (Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg)>;
6432 def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0, (VTI.Pred VCCR:$pred)),
6433 (Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg)>;
6512 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (AVTI.Pred VCCR:$pred))),
6514 ARMVCCThen, VCCR:$pred, zero_reg))>;
6530 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred)),
6532 (i32 imm:$offset), ARMVCCThen, VCCR:$pred, zero_reg)>;
6538 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred))),
6540 (i32 imm:$offset), ARMVCCThen, VCCR:$pred, zero_reg))>;
6794 def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
6795 (v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
6796 def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))),
6797 (v8i16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
6798 def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
6799 (v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
6800 def : Pat<(v2i64 (vselect (v2i1 VCCR:$pred), (v2i64 MQPR:$v1), (v2i64 MQPR:$v2))),
6801 (v2i64 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
6803 def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
6804 (v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
6805 def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
6806 (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
6807 def : Pat<(v2f64 (vselect (v2i1 VCCR:$pred), (v2f64 MQPR:$v1), (v2f64 MQPR:$v2))),
6808 (v2f64 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
6810 def : Pat<(v16i8 (vselect (v16i8 MQPR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
6812 (MVE_VCMPi8 (v16i8 MQPR:$pred), (MVE_VMOVimmi8 0), ARMCCne), zero_reg))>;
6813 def : Pat<(v8i16 (vselect (v8i16 MQPR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))),
6815 (MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), ARMCCne), zero_reg))>;
6816 def : Pat<(v4i32 (vselect (v4i32 MQPR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
6818 (MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), ARMCCne), zero_reg))>;
6820 def : Pat<(v8f16 (vselect (v8i16 MQPR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
6822 (MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), ARMCCne), zero_reg))>;
6823 def : Pat<(v4f32 (vselect (v4i32 MQPR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
6825 (MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), ARMCCne), zero_reg))>;
6828 def : Pat<(v16i8 (zext (v16i1 VCCR:$pred))),
6829 (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6830 def : Pat<(v8i16 (zext (v8i1 VCCR:$pred))),
6831 (v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6832 def : Pat<(v4i32 (zext (v4i1 VCCR:$pred))),
6833 (v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6834 def : Pat<(v2i64 (zext (v2i1 VCCR:$pred))),
6835 (v2i64 (MVE_VPSEL (MVE_VMOVimmi64 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6837 def : Pat<(v16i8 (sext (v16i1 VCCR:$pred))),
6838 (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6839 def : Pat<(v8i16 (sext (v8i1 VCCR:$pred))),
6840 (v8i16 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6841 def : Pat<(v4i32 (sext (v4i1 VCCR:$pred))),
6842 (v4i32 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6843 def : Pat<(v2i64 (sext (v2i1 VCCR:$pred))),
6844 (v2i64 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6846 def : Pat<(v16i8 (anyext (v16i1 VCCR:$pred))),
6847 (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6848 def : Pat<(v8i16 (anyext (v8i1 VCCR:$pred))),
6849 (v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6850 def : Pat<(v4i32 (anyext (v4i1 VCCR:$pred))),
6851 (v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6852 def : Pat<(v2i64 (anyext (v2i1 VCCR:$pred))),
6853 (v2i64 (MVE_VPSEL (MVE_VMOVimmi64 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
6859 def : Pat<(v4f32 (uint_to_fp (v4i1 VCCR:$pred))),
6860 (v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 112)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred, zero_reg))>;
6862 def : Pat<(v8f16 (uint_to_fp (v8i1 VCCR:$pred))),
6863 (v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2620)), (v8f16 (MVE_VMOVimmi16 0)), ARMVCCNone, VCCR:$pred, zero_reg))>;
6865 def : Pat<(v4f32 (sint_to_fp (v4i1 VCCR:$pred))),
6866 (v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 240)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred, zero_reg))>;
6868 def : Pat<(v8f16 (sint_to_fp (v8i1 VCCR:$pred))),
6869 (v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2748)), (v8f16 (MVE_VMOVimmi16 0)), ARMVCCNone, VCCR:$pred, zero_reg))>;
6894 def : Pat<(v2i1 (xor (v2i1 VCCR:$pred), (v2i1 (predicate_cast (i32 65535))))),
6895 (v2i1 (MVE_VPNOT (v2i1 VCCR:$pred)))>;
6896 def : Pat<(v4i1 (xor (v4i1 VCCR:$pred), (v4i1 (predicate_cast (i32 65535))))),
6897 (v4i1 (MVE_VPNOT (v4i1 VCCR:$pred)))>;
6898 def : Pat<(v8i1 (xor (v8i1 VCCR:$pred), (v8i1 (predicate_cast (i32 65535))))),
6899 (v8i1 (MVE_VPNOT (v8i1 VCCR:$pred)))>;
6900 def : Pat<(v16i1 (xor (v16i1 VCCR:$pred), (v16i1 (predicate_cast (i32 65535))))),
6901 (v16i1 (MVE_VPNOT (v16i1 VCCR:$pred)))>;
6987 def MVE_LCTP : MVE_loltp_end<(outs), (ins pred:$p), "lctp${p}", ""> {
7051 def aligned_maskedloadvi8 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7052 (masked_ld node:$ptr, undef, node:$pred, node:$passthru), [{
7056 def aligned_sextmaskedloadvi8 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7057 (aligned_maskedloadvi8 node:$ptr, node:$pred, node:$passthru), [{
7060 def aligned_zextmaskedloadvi8 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7061 (aligned_maskedloadvi8 node:$ptr, node:$pred, node:$passthru), [{
7064 def aligned_extmaskedloadvi8 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7065 (aligned_maskedloadvi8 node:$ptr, node:$pred, node:$passthru), [{
7070 def aligned_maskedloadvi16: PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7071 (masked_ld node:$ptr, undef, node:$pred, node:$passthru), [{
7076 def aligned_sextmaskedloadvi16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7077 (aligned_maskedloadvi16 node:$ptr, node:$pred, node:$passthru), [{
7080 def aligned_zextmaskedloadvi16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7081 (aligned_maskedloadvi16 node:$ptr, node:$pred, node:$passthru), [{
7084 def aligned_extmaskedloadvi16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7085 (aligned_maskedloadvi16 node:$ptr, node:$pred, node:$passthru), [{
7090 def aligned_maskedloadvi32: PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
7091 (masked_ld node:$ptr, undef, node:$pred, node:$passthru), [{
7097 def aligned_maskedstvi8 : PatFrag<(ops node:$val, node:$ptr, node:$pred),
7098 (masked_st node:$val, node:$ptr, undef, node:$pred), [{
7101 def aligned_maskedstvi16 : PatFrag<(ops node:$val, node:$ptr, node:$pred),
7102 (masked_st node:$val, node:$ptr, undef, node:$pred), [{
7107 def aligned_maskedstvi32 : PatFrag<(ops node:$val, node:$ptr, node:$pred),
7108 (masked_st node:$val, node:$ptr, undef, node:$pred), [{
7184 def truncmaskedst : PatFrag<(ops node:$val, node:$base, node:$pred),
7185 (masked_st node:$val, node:$base, undef, node:$pred), [{
7188 def aligned_truncmaskedstvi8 : PatFrag<(ops node:$val, node:$base, node:$pred),
7189 (truncmaskedst node:$val, node:$base, node:$pred), [{
7192 def aligned_truncmaskedstvi16 : PatFrag<(ops node:$val, node:$base, node:$pred),
7193 (truncmaskedst node:$val, node:$base, node:$pred), [{
7198 def pre_truncmaskedst : PatFrag<(ops node:$val, node:$base, node:$offset, node:$pred),
7199 (masked_st node:$val, node:$base, node:$offset, node:$pred), [{
7203 def aligned_pre_truncmaskedstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset, node:$pred),
7204 (pre_truncmaskedst node:$val, node:$base, node:$offset, node:$pred), [{
7207 def aligned_pre_truncmaskedstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset, node:$pred),
7208 (pre_truncmaskedst node:$val, node:$base, node:$offset, node:$pred), [{
7238 : Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr, VCCR:$pred),
7239 (RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
7259 : Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr, VCCR:$pred, (Ty (ARMvmovImm (i32 0))))),
7260 (Ty (RegImmInst t2addrmode_imm7<shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg))>;
7280 : Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr, VCCR:$pred),
7281 (Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
7410 def : Pat<(!cast<PatFrag>("aligned_truncmaskedst"#Amble) (VT MQPR:$val), taddrmode_imm7<Shift>:$addr, VCCR:$pred),
7411 (!cast<Instruction>(StoreInst) MQPR:$val, taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
7412 def : Pat<(!cast<PatFrag>("aligned_post_truncmaskedst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, VCCR:$pred),
7413 (!cast<Instruction>(StoreInst#"_post") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
7414 def : Pat<(!cast<PatFrag>("aligned_pre_truncmaskedst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, VCCR:$pred),
7415 (!cast<Instruction>(StoreInst#"_pre") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
7426 def : Pat<(VT (!cast<PatFrag>("aligned_extmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
7427 (VT (LoadUInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg))>;
7428 def : Pat<(VT (!cast<PatFrag>("aligned_sextmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
7429 (VT (LoadSInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg))>;
7430 def : Pat<(VT (!cast<PatFrag>("aligned_zextmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
7431 (VT (LoadUInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg))>;