Lines Matching refs:sra
402 (i32 (sra node:$a, (i32 16)))>;
407 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>;
409 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>;
411 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>;
771 [shl, srl, sra, rotr]> {
782 [shl, srl, sra, rotr]> {
793 [shl,srl,sra,rotr]> {
804 [shl,srl,sra,rotr]> {
4158 def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),
4162 def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
4166 def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
4170 def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
4793 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4797 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4816 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4822 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4835 (sra GPRnopc:$src2, imm16_31:$sh)),