Lines Matching refs:RdLo
4301 bits<4> RdLo;
4306 let Inst{15-12} = RdLo;
4313 bits<4> RdLo;
4318 let Inst{15-12} = RdLo;
4384 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4386 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4387 [(set GPR:$RdLo, GPR:$RdHi,
4392 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4394 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4395 [(set GPR:$RdLo, GPR:$RdHi,
4400 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
4401 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4404 [(set GPR:$RdLo, GPR:$RdHi,
4406 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4410 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4413 [(set GPR:$RdLo, GPR:$RdHi,
4415 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4422 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4424 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4425 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4427 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4429 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4430 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4433 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
4436 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4437 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4439 bits<4> RdLo;
4444 let Inst{15-12} = RdLo;
4450 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
4451 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4454 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4458 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4461 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4610 (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4612 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4613 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4666 bits<4> RdLo;
4669 let Inst{15-12} = RdLo;
4684 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4687 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
4688 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4691 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4694 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
4695 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
6447 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6448 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6450 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6451 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6453 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6454 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6456 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6457 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,