1171   if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()  in ARMTargetLowering()
1221   if (!Subtarget->hasV6Ops())  in ARMTargetLowering()
1376       (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {  in ARMTargetLowering()
1403   if (!Subtarget->hasV6Ops()) {  in ARMTargetLowering()
1605   if (Subtarget->hasV6Ops())  in ARMTargetLowering()
1610   if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||  in ARMTargetLowering()
1960       (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? Align(8) : Align(4));  in shouldAlignPointerArgs()
4277     assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&  in LowerATOMIC_FENCE()
5082   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP() || Subtarget->isThumb1Only())  in LowerADDSUBSAT()
5433   if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())  in LowerSELECT_CC()
13032   if (Subtarget->hasV6Ops() && Subtarget->hasDSP() && Subtarget->useMulOps() &&  in AddCombineTo64bitMLAL()
13079   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())  in AddCombineTo64bitUMAAL()
13127   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())  in PerformUMLALCombine()
14465   if (!Subtarget->hasV6Ops() ||  in PerformORCombineToSMULWBT()
17935   if ((Subtarget->isThumb() || !Subtarget->hasV6Ops()) &&  in PerformMinMaxToSatCombine()
20321   if (!Subtarget->hasV6Ops())  in ExpandInlineAsm()
21272     if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {  in makeDMB()
21348     has64BitAtomicStore = Subtarget->hasV6Ops();  in shouldExpandAtomicStoreInIR()
21370     has64BitAtomicLoad = Subtarget->hasV6Ops();  in shouldExpandAtomicLoadInIR()
21391     hasAtomicRMW = Subtarget->hasV6Ops();  in shouldExpandAtomicRMWInIR()
21421     HasAtomicCmpXchg = Subtarget->hasV6Ops();  in shouldExpandAtomicCmpXchgInIR()