Lines Matching refs:DCI
12592 TargetLowering::DAGCombinerInfo &DCI, in combineSelectAndUse() argument
12594 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse()
12618 TargetLowering::DAGCombinerInfo &DCI) { in combineSelectAndUseCommutative() argument
12622 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
12625 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
12643 TargetLowering::DAGCombinerInfo &DCI, in AddCombineToVPADD() argument
12655 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADD()
12671 TargetLowering::DAGCombinerInfo &DCI, in AddCombineVUZPToVPADDL() argument
12695 SelectionDAG &DAG = DCI.DAG; in AddCombineVUZPToVPADDL()
12724 TargetLowering::DAGCombinerInfo &DCI, in AddCombineBUILD_VECTORToVPADDL() argument
12728 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineBUILD_VECTORToVPADDL()
12789 SelectionDAG &DAG = DCI.DAG; in AddCombineBUILD_VECTORToVPADDL()
12828 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64BitSMLAL16() argument
12863 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64BitSMLAL16()
12905 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64bitMLAL() argument
12961 return AddCombineTo64BitSMLAL16(AddcSubcNode, AddeSubeNode, DCI, Subtarget); in AddCombineTo64bitMLAL()
13021 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64bitMLAL()
13071 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64bitUMAAL() argument
13080 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget); in AddCombineTo64bitUMAAL()
13097 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget); in AddCombineTo64bitUMAAL()
13109 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64bitUMAAL()
13148 TargetLowering::DAGCombinerInfo &DCI, in PerformAddcSubcCombine() argument
13150 SelectionDAG &DAG(DCI.DAG); in PerformAddcSubcCombine()
13159 return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2)); in PerformAddcSubcCombine()
13181 TargetLowering::DAGCombinerInfo &DCI, in PerformAddeSubeCombine() argument
13184 SelectionDAG &DAG = DCI.DAG; in PerformAddeSubeCombine()
13203 return AddCombineTo64bitMLAL(N, DCI, Subtarget); in PerformAddeSubeCombine()
13209 TargetLowering::DAGCombinerInfo &DCI, in PerformSELECTCombine() argument
13300 LHS = DCI.DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); in PerformSELECTCombine()
13304 DCI.DAG.getNode(Opcode, dl, MVT::i32, LHS, RHS->getOperand(0)); in PerformSELECTCombine()
13308 Reduction = DCI.DAG.getNode(ISD::TRUNCATE, dl, VectorScalarType, Reduction); in PerformSELECTCombine()
13428 TargetLowering::DAGCombinerInfo &DCI, in PerformVSELECTCombine() argument
13433 if (SDValue V = PerformVQDMULHCombine(N, DCI.DAG)) in PerformVSELECTCombine()
13463 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS); in PerformVSELECTCombine()
13468 TargetLowering::DAGCombinerInfo &DCI, in PerformVSetCCToVCTPCombine() argument
13476 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformVSetCCToVCTPCombine()
13497 SDValue Op1S = DCI.DAG.getSplatValue(Op1); in PerformVSetCCToVCTPCombine()
13520 return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, in PerformVSetCCToVCTPCombine()
13521 DCI.DAG.getConstant(Opc, DL, MVT::i32), in PerformVSetCCToVCTPCombine()
13522 DCI.DAG.getZExtOrTrunc(Op1S, DL, MVT::i32)); in PerformVSetCCToVCTPCombine()
13529 TargetLowering::DAGCombinerInfo &DCI, in PerformADDECombine() argument
13533 return PerformAddeSubeCombine(N, DCI, Subtarget); in PerformADDECombine()
13536 if (DCI.isBeforeLegalize()) return SDValue(); in PerformADDECombine()
13538 return AddCombineTo64bitUMAAL(N, DCI, Subtarget); in PerformADDECombine()
13546 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombineWithOperands() argument
13549 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13553 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13555 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI, in PerformADDCombineWithOperands()
13561 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI)) in PerformADDCombineWithOperands()
13915 TargetLowering::DAGCombinerInfo &DCI, in PerformSHLSimplify() argument
13918 if (DCI.isBeforeLegalize()) in PerformSHLSimplify()
14005 SelectionDAG &DAG = DCI.DAG; in PerformSHLSimplify()
14023 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombine() argument
14029 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformADDCombine()
14032 if (SDValue Result = PerformADDVecReduce(N, DCI.DAG, Subtarget)) in PerformADDCombine()
14036 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget)) in PerformADDCombine()
14040 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); in PerformADDCombine()
14066 TargetLowering::DAGCombinerInfo &DCI, in PerformSUBCombine() argument
14073 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI)) in PerformSUBCombine()
14076 if (SDValue R = PerformSubCSINCCombine(N, DCI.DAG)) in PerformSUBCombine()
14097 SDValue Negate = DCI.DAG.getNode(ISD::SUB, dl, MVT::i32, in PerformSUBCombine()
14098 DCI.DAG.getConstant(0, dl, MVT::i32), in PerformSUBCombine()
14100 return DCI.DAG.getNode(ARMISD::VDUP, dl, N->getValueType(0), Negate); in PerformSUBCombine()
14119 TargetLowering::DAGCombinerInfo &DCI, in PerformVMULCombine() argument
14124 SelectionDAG &DAG = DCI.DAG; in PerformVMULCombine()
14215 TargetLowering::DAGCombinerInfo &DCI, in PerformMULCombine() argument
14217 SelectionDAG &DAG = DCI.DAG; in PerformMULCombine()
14226 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMULCombine()
14230 return PerformVMULCombine(N, DCI, Subtarget); in PerformMULCombine()
14296 DCI.CombineTo(N, Res, false); in PerformMULCombine()
14301 TargetLowering::DAGCombinerInfo &DCI, in CombineANDShift() argument
14304 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in CombineANDShift()
14342 SelectionDAG &DAG = DCI.DAG; in CombineANDShift()
14413 TargetLowering::DAGCombinerInfo &DCI, in PerformANDCombine() argument
14419 SelectionDAG &DAG = DCI.DAG; in PerformANDCombine()
14447 if (SDValue Result = combineSelectAndUseCommutative(N, true, DCI)) in PerformANDCombine()
14450 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformANDCombine()
14455 if (SDValue Result = CombineANDShift(N, DCI, Subtarget)) in PerformANDCombine()
14463 TargetLowering::DAGCombinerInfo &DCI, in PerformORCombineToSMULWBT() argument
14500 SelectionDAG &DAG = DCI.DAG; in PerformORCombineToSMULWBT()
14523 TargetLowering::DAGCombinerInfo &DCI, in PerformORCombineToBFI() argument
14532 SelectionDAG &DAG = DCI.DAG; in PerformORCombineToBFI()
14574 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14601 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14618 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14639 DCI.CombineTo(N, Res, false); in PerformORCombineToBFI()
14706 TargetLowering::DAGCombinerInfo &DCI, in PerformORCombine() argument
14712 SelectionDAG &DAG = DCI.DAG; in PerformORCombine()
14743 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI)) in PerformORCombine()
14745 if (SDValue Result = PerformORCombineToSMULWBT(N, DCI, Subtarget)) in PerformORCombine()
14795 if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget)) in PerformORCombine()
14799 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformORCombine()
14806 TargetLowering::DAGCombinerInfo &DCI, in PerformXORCombine() argument
14809 SelectionDAG &DAG = DCI.DAG; in PerformXORCombine()
14816 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI)) in PerformXORCombine()
14819 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformXORCombine()
15054 TargetLowering::DAGCombinerInfo &DCI, in PerformVMOVRRDCombine() argument
15059 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); in PerformVMOVRRDCombine()
15070 SelectionDAG &DAG = DCI.DAG; in PerformVMOVRRDCombine()
15086 if (DCI.DAG.getDataLayout().isBigEndian()) in PerformVMOVRRDCombine()
15088 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); in PerformVMOVRRDCombine()
15119 return DCI.DAG.getMergeValues({Op0, Op1}, SDLoc(N)); in PerformVMOVRRDCombine()
15137 return DCI.DAG.getMergeValues({Op0, Op1}, SDLoc(N)); in PerformVMOVRRDCombine()
15162 TargetLowering::DAGCombinerInfo &DCI) { in PerformVMOVhrCombine() argument
15186 DCI.DAG.getNode(ISD::CopyFromReg, SDLoc(N), in PerformVMOVhrCombine()
15187 DCI.DAG.getVTList(ArrayRef(OutTys, HasGlue ? 3 : 2)), in PerformVMOVhrCombine()
15191 DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), NewCopy.getValue(0)); in PerformVMOVhrCombine()
15192 DCI.DAG.ReplaceAllUsesOfValueWith(Copy.getValue(1), NewCopy.getValue(1)); in PerformVMOVhrCombine()
15194 DCI.DAG.ReplaceAllUsesOfValueWith(Copy.getValue(2), in PerformVMOVhrCombine()
15206 DCI.DAG.getLoad(N->getValueType(0), SDLoc(N), LN0->getChain(), in PerformVMOVhrCombine()
15208 DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Load.getValue(0)); in PerformVMOVhrCombine()
15209 DCI.DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Load.getValue(1)); in PerformVMOVhrCombine()
15216 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo(); in PerformVMOVhrCombine()
15217 if (TLI.SimplifyDemandedBits(Op0, DemandedMask, DCI)) in PerformVMOVhrCombine()
15271 TargetLowering::DAGCombinerInfo &DCI, in PerformBUILD_VECTORCombine() argument
15277 SelectionDAG &DAG = DCI.DAG; in PerformBUILD_VECTORCombine()
15294 DCI.AddToWorklist(V.getNode()); in PerformBUILD_VECTORCombine()
15303 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in PerformARMBUILD_VECTORCombine() argument
15356 SelectionDAG &DAG = DCI.DAG; in PerformARMBUILD_VECTORCombine()
15382 DCI.AddToWorklist(V.getNode()); in PerformARMBUILD_VECTORCombine()
15389 DCI.AddToWorklist(Vec.getNode()); in PerformARMBUILD_VECTORCombine()
15394 PerformPREDICATE_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in PerformPREDICATE_CASTCombine() argument
15404 return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0)); in PerformPREDICATE_CASTCombine()
15411 DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0)); in PerformPREDICATE_CASTCombine()
15412 SDValue C = DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, in PerformPREDICATE_CASTCombine()
15413 DCI.DAG.getConstant(65535, dl, MVT::i32)); in PerformPREDICATE_CASTCombine()
15414 return DCI.DAG.getNode(ISD::XOR, dl, VT, X, C); in PerformPREDICATE_CASTCombine()
15420 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo(); in PerformPREDICATE_CASTCombine()
15421 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI)) in PerformPREDICATE_CASTCombine()
15485 TargetLowering::DAGCombinerInfo &DCI) { in PerformInsertEltCombine() argument
15494 SelectionDAG &DAG = DCI.DAG; in PerformInsertEltCombine()
15501 DCI.AddToWorklist(Vec.getNode()); in PerformInsertEltCombine()
15502 DCI.AddToWorklist(V.getNode()); in PerformInsertEltCombine()
15513 PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in PerformExtractEltToVMOVRRD() argument
15517 if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 || in PerformExtractEltToVMOVRRD()
15518 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(MVT::f64)) in PerformExtractEltToVMOVRRD()
15563 SDValue F64 = DCI.DAG.getNode( in PerformExtractEltToVMOVRRD()
15565 DCI.DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v2f64, Op0), in PerformExtractEltToVMOVRRD()
15566 DCI.DAG.getConstant(Ext.getConstantOperandVal(1) / 2, dl, MVT::i32)); in PerformExtractEltToVMOVRRD()
15568 DCI.DAG.getNode(ARMISD::VMOVRRD, dl, {MVT::i32, MVT::i32}, F64); in PerformExtractEltToVMOVRRD()
15570 DCI.CombineTo(OtherExt.getNode(), SDValue(VMOVRRD.getNode(), 1)); in PerformExtractEltToVMOVRRD()
15575 TargetLowering::DAGCombinerInfo &DCI, in PerformExtractEltCombine() argument
15585 return DCI.DAG.getNode(ARMISD::VMOVhr, dl, VT, X); in PerformExtractEltCombine()
15587 return DCI.DAG.getNode(ARMISD::VMOVrh, dl, VT, X); in PerformExtractEltCombine()
15589 return DCI.DAG.getNode(ISD::BITCAST, dl, VT, X); in PerformExtractEltCombine()
15618 if (SDValue R = PerformExtractEltToVMOVRRD(N, DCI)) in PerformExtractEltCombine()
15628 return DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Op0.getOperand(Vec), in PerformExtractEltCombine()
15629 DCI.DAG.getConstant(SubIdx, dl, MVT::i32)); in PerformExtractEltCombine()
15650 PerformInsertSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in PerformInsertSubvectorCombine() argument
15659 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(VecVT) || in PerformInsertSubvectorCombine()
15660 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(SubVT)) in PerformInsertSubvectorCombine()
15680 Hi = DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, Vec, in PerformInsertSubvectorCombine()
15681 DCI.DAG.getVectorIdxConstant(NumSubElts, DL)); in PerformInsertSubvectorCombine()
15683 Lo = DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, Vec, in PerformInsertSubvectorCombine()
15684 DCI.DAG.getVectorIdxConstant(0, DL)); in PerformInsertSubvectorCombine()
15687 return DCI.DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, Lo, Hi); in PerformInsertSubvectorCombine()
15790 TargetLowering::DAGCombinerInfo &DCI) { in TryCombineBaseUpdate() argument
15791 SelectionDAG &DAG = DCI.DAG; in TryCombineBaseUpdate()
16082 DCI.CombineTo(N, NewResults); in TryCombineBaseUpdate()
16083 DCI.CombineTo(User.N, SDValue(UpdN.getNode(), NumResultVecs)); in TryCombineBaseUpdate()
16157 TargetLowering::DAGCombinerInfo &DCI) { in CombineBaseUpdate() argument
16178 getPointerConstIncrement(User->getOpcode(), Addr, Inc, DCI.DAG); in CombineBaseUpdate()
16190 getPointerConstIncrement(Addr->getOpcode(), Base, CInc, DCI.DAG); in CombineBaseUpdate()
16201 getPointerConstIncrement(User->getOpcode(), Base, UserInc, DCI.DAG); in CombineBaseUpdate()
16207 SDValue NewInc = DCI.DAG.getConstant(NewConstInc, SDLoc(N), MVT::i32); in CombineBaseUpdate()
16225 if (TryCombineBaseUpdate(Target, User, /*SimpleConstIncOnly=*/true, DCI)) in CombineBaseUpdate()
16239 if (TryCombineBaseUpdate(Target, User, /*SimpleConstIncOnly=*/false, DCI)) in CombineBaseUpdate()
16246 TargetLowering::DAGCombinerInfo &DCI) { in PerformVLDCombine() argument
16247 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformVLDCombine()
16250 return CombineBaseUpdate(N, DCI); in PerformVLDCombine()
16254 TargetLowering::DAGCombinerInfo &DCI) { in PerformMVEVLDCombine() argument
16255 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMVEVLDCombine()
16258 SelectionDAG &DAG = DCI.DAG; in PerformMVEVLDCombine()
16364 DCI.CombineTo(N, NewResults); in PerformMVEVLDCombine()
16365 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); in PerformMVEVLDCombine()
16377 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in CombineVLDDUP() argument
16378 SelectionDAG &DAG = DCI.DAG; in CombineVLDDUP()
16439 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); in CombineVLDDUP()
16448 DCI.CombineTo(VLD, VLDDupResults); in CombineVLDDUP()
16456 TargetLowering::DAGCombinerInfo &DCI, in PerformVDUPLANECombine() argument
16465 if (!DCI.DAG.getTargetLoweringInfo().isTypeLegal(ExtractVT)) in PerformVDUPLANECombine()
16467 SDValue Extract = DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ExtractVT, in PerformVDUPLANECombine()
16469 return DCI.DAG.getNode(ARMISD::VDUP, SDLoc(N), VT, Extract); in PerformVDUPLANECombine()
16474 if (CombineVLDDUP(N, DCI)) in PerformVDUPLANECombine()
16494 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); in PerformVDUPLANECombine()
16537 TargetLowering::DAGCombinerInfo &DCI, in PerformLOADCombine() argument
16543 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformLOADCombine()
16544 return CombineBaseUpdate(N, DCI); in PerformLOADCombine()
16807 TargetLowering::DAGCombinerInfo &DCI, in PerformSTORECombine() argument
16816 if (SDValue Store = PerformTruncatingStoreCombine(St, DCI.DAG)) in PerformSTORECombine()
16820 if (SDValue NewToken = PerformSplittingToNarrowingStores(St, DCI.DAG)) in PerformSTORECombine()
16824 if (SDValue NewChain = PerformExtractFpToIntStores(St, DCI.DAG)) in PerformSTORECombine()
16827 PerformSplittingMVETruncToNarrowingStores(St, DCI.DAG)) in PerformSTORECombine()
16838 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine()
16861 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine()
16872 DCI.AddToWorklist(Vec.getNode()); in PerformSTORECombine()
16873 DCI.AddToWorklist(ExtElt.getNode()); in PerformSTORECombine()
16874 DCI.AddToWorklist(V.getNode()); in PerformSTORECombine()
16882 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformSTORECombine()
16883 return CombineBaseUpdate(N, DCI); in PerformSTORECombine()
17389 TargetLowering::DAGCombinerInfo &DCI) { in PerformVMOVNCombine() argument
17407 return DCI.DAG.getNode(Op1->getOpcode(), SDLoc(Op1), N->getValueType(0), in PerformVMOVNCombine()
17419 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo(); in PerformVMOVNCombine()
17420 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI)) in PerformVMOVNCombine()
17422 if (TLI.SimplifyDemandedVectorElts(Op1, Op1DemandedElts, DCI)) in PerformVMOVNCombine()
17429 TargetLowering::DAGCombinerInfo &DCI) { in PerformVQMOVNCombine() argument
17438 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo(); in PerformVQMOVNCombine()
17439 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI)) in PerformVQMOVNCombine()
17445 TargetLowering::DAGCombinerInfo &DCI) { in PerformVQDMULHCombine() argument
17457 SDValue NewBinOp = DCI.DAG.getNode(N->getOpcode(), DL, VT, in PerformVQDMULHCombine()
17460 return DCI.DAG.getVectorShuffle(VT, DL, NewBinOp, UndefV, Shuf0->getMask()); in PerformVQDMULHCombine()
17495 DAGCombinerInfo &DCI) const { in PerformIntrinsicCombine()
17496 SelectionDAG &DAG = DCI.DAG; in PerformIntrinsicCombine()
17662 if (SimplifyDemandedBits(N->getOperand(3), DemandedMask, DCI)) in PerformIntrinsicCombine()
17679 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformIntrinsicCombine()
17722 TargetLowering::DAGCombinerInfo &DCI, in PerformShiftCombine() argument
17724 SelectionDAG &DAG = DCI.DAG; in PerformShiftCombine()
17730 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformShiftCombine()
18221 TargetLowering::DAGCombinerInfo &DCI, in PerformHWLoopCombine() argument
18286 SelectionDAG &DAG = DCI.DAG; in PerformHWLoopCombine()
18570 TargetLowering::DAGCombinerInfo &DCI, in PerformBITCASTCombine() argument
18572 SelectionDAG &DAG = DCI.DAG; in PerformBITCASTCombine()
18599 if (SDValue R = PerformExtractEltToVMOVRRD(N, DCI)) in PerformBITCASTCombine()
18608 SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const { in PerformMVETruncCombine()
18609 SelectionDAG &DAG = DCI.DAG; in PerformMVETruncCombine()
18678 if (!DCI.isAfterLegalizeDAG()) in PerformMVETruncCombine()
18777 SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const { in PerformMVEExtCombine()
18778 SelectionDAG &DAG = DCI.DAG; in PerformMVEExtCombine()
18844 if (!DCI.isAfterLegalizeDAG()) in PerformMVEExtCombine()
18881 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
18885 case ISD::SELECT: return PerformSELECTCombine(N, DCI, Subtarget); in PerformDAGCombine()
18886 case ISD::VSELECT: return PerformVSELECTCombine(N, DCI, Subtarget); in PerformDAGCombine()
18887 case ISD::SETCC: return PerformVSetCCToVCTPCombine(N, DCI, Subtarget); in PerformDAGCombine()
18888 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget); in PerformDAGCombine()
18889 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18890 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); in PerformDAGCombine()
18891 case ISD::SUB: return PerformSUBCombine(N, DCI, Subtarget); in PerformDAGCombine()
18892 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); in PerformDAGCombine()
18893 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); in PerformDAGCombine()
18894 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget); in PerformDAGCombine()
18895 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget); in PerformDAGCombine()
18897 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget); in PerformDAGCombine()
18899 case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget); in PerformDAGCombine()
18900 case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget); in PerformDAGCombine()
18901 case ARMISD::BFI: return PerformBFICombine(N, DCI.DAG); in PerformDAGCombine()
18902 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget); in PerformDAGCombine()
18903 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); in PerformDAGCombine()
18904 case ARMISD::VMOVhr: return PerformVMOVhrCombine(N, DCI); in PerformDAGCombine()
18905 case ARMISD::VMOVrh: return PerformVMOVrhCombine(N, DCI.DAG); in PerformDAGCombine()
18906 case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget); in PerformDAGCombine()
18907 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget); in PerformDAGCombine()
18908 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); in PerformDAGCombine()
18910 return PerformExtractEltCombine(N, DCI, Subtarget); in PerformDAGCombine()
18911 case ISD::SIGN_EXTEND_INREG: return PerformSignExtendInregCombine(N, DCI.DAG); in PerformDAGCombine()
18912 case ISD::INSERT_SUBVECTOR: return PerformInsertSubvectorCombine(N, DCI); in PerformDAGCombine()
18913 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); in PerformDAGCombine()
18914 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget); in PerformDAGCombine()
18915 case ARMISD::VDUP: return PerformVDUPCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18918 return PerformVCVTCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18920 return PerformFADDCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18922 return PerformVMulVCTPCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18924 return PerformIntrinsicCombine(N, DCI); in PerformDAGCombine()
18928 return PerformShiftCombine(N, DCI, Subtarget); in PerformDAGCombine()
18932 return PerformExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18934 return PerformFPExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18939 return PerformMinMaxCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18941 return PerformCMOVCombine(N, DCI.DAG); in PerformDAGCombine()
18943 return PerformBRCONDCombine(N, DCI.DAG); in PerformDAGCombine()
18945 return PerformCMPZCombine(N, DCI.DAG); in PerformDAGCombine()
18949 return PerformCSETCombine(N, DCI.DAG); in PerformDAGCombine()
18951 return PerformLOADCombine(N, DCI, Subtarget); in PerformDAGCombine()
18956 return PerformVLDCombine(N, DCI); in PerformDAGCombine()
18958 return PerformARMBUILD_VECTORCombine(N, DCI); in PerformDAGCombine()
18960 return PerformBITCASTCombine(N, DCI, Subtarget); in PerformDAGCombine()
18962 return PerformPREDICATE_CASTCombine(N, DCI); in PerformDAGCombine()
18964 return PerformVECTOR_REG_CASTCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18966 return PerformMVETruncCombine(N, DCI); in PerformDAGCombine()
18969 return PerformMVEExtCombine(N, DCI); in PerformDAGCombine()
18971 return PerformVCMPCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18973 return PerformVECREDUCE_ADDCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
18986 return PerformReduceShuffleCombine(N, DCI.DAG); in PerformDAGCombine()
18988 return PerformVMOVNCombine(N, DCI); in PerformDAGCombine()
18991 return PerformVQMOVNCombine(N, DCI); in PerformDAGCombine()
18993 return PerformVQDMULHCombine(N, DCI); in PerformDAGCombine()
18997 return PerformLongShiftCombine(N, DCI.DAG); in PerformDAGCombine()
19001 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformDAGCombine()
19008 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformDAGCombine()
19019 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || in PerformDAGCombine()
19020 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) in PerformDAGCombine()
19029 if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) || in PerformDAGCombine()
19030 (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI))) in PerformDAGCombine()
19039 if ((SimplifyDemandedBits(N->getOperand(0), HighMask, DCI)) || in PerformDAGCombine()
19040 (SimplifyDemandedBits(N->getOperand(1), LowMask, DCI))) in PerformDAGCombine()
19047 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || in PerformDAGCombine()
19048 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) in PerformDAGCombine()
19058 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || in PerformDAGCombine()
19059 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) in PerformDAGCombine()
19089 return PerformVLDCombine(N, DCI); in PerformDAGCombine()
19094 return PerformMVEVLDCombine(N, DCI); in PerformDAGCombine()