Lines Matching refs:Cnt
6610 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { in getVShiftImm() argument
6623 Cnt = SplatBits.getSExtValue(); in getVShiftImm()
6631 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { in isVShiftLImm() argument
6634 if (!getVShiftImm(Op, ElementBits, Cnt)) in isVShiftLImm()
6636 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits); in isVShiftLImm()
6646 int64_t &Cnt) { in isVShiftRImm() argument
6649 if (!getVShiftImm(Op, ElementBits, Cnt)) in isVShiftRImm()
6652 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits)); in isVShiftRImm()
6653 if (Cnt >= -(isNarrow ? ElementBits / 2 : ElementBits) && Cnt <= -1) { in isVShiftRImm()
6654 Cnt = -Cnt; in isVShiftRImm()
6664 int64_t Cnt; in LowerShift() local
6676 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) in LowerShift()
6678 DAG.getConstant(Cnt, dl, MVT::i32)); in LowerShift()
6686 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { in LowerShift()
6690 DAG.getConstant(Cnt, dl, MVT::i32)); in LowerShift()
17523 int64_t Cnt; in PerformIntrinsicCombine() local
17529 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { in PerformIntrinsicCombine()
17533 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { in PerformIntrinsicCombine()
17542 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) in PerformIntrinsicCombine()
17548 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) in PerformIntrinsicCombine()
17553 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) in PerformIntrinsicCombine()
17565 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) in PerformIntrinsicCombine()
17619 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32)); in PerformIntrinsicCombine()
17624 int64_t Cnt; in PerformIntrinsicCombine() local
17627 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) in PerformIntrinsicCombine()
17629 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) in PerformIntrinsicCombine()
17638 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformIntrinsicCombine()
17768 int64_t Cnt; in PerformShiftCombine() local
17774 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) { in PerformShiftCombine()
17777 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformShiftCombine()
17783 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { in PerformShiftCombine()
17788 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformShiftCombine()