807       case ARM::R4:  in emitPrologue()
847       case ARM::R4:  in emitPrologue()
980       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)  in emitPrologue()
988       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)  in emitPrologue()
992       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), ARM::R4)  in emitPrologue()
993           .addReg(ARM::R4)  in emitPrologue()
1008           .addReg(ARM::R4, RegState::Implicit)  in emitPrologue()
1019           .addReg(ARM::R4, RegState::Implicit)  in emitPrologue()
1027                 .addReg(ARM::R4, RegState::Kill)  in emitPrologue()
1140       case ARM::R4:  in emitPrologue()
1236       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)  in emitPrologue()
1239       emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,  in emitPrologue()
1242           .addReg(ARM::R4, RegState::Kill)  in emitPrologue()
1357           assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&  in emitEpilogue()
1359           emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,  in emitEpilogue()
1362               .addReg(ARM::R4)  in emitEpilogue()
1762   BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)  in emitAlignedDPRCS2Spills()
1774   emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);  in emitAlignedDPRCS2Spills()
1782                                 .addReg(ARM::R4)  in emitAlignedDPRCS2Spills()
1797     BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)  in emitAlignedDPRCS2Spills()
1798         .addReg(ARM::R4, RegState::Kill)  in emitAlignedDPRCS2Spills()
1817         .addReg(ARM::R4)  in emitAlignedDPRCS2Spills()
1832         .addReg(ARM::R4)  in emitAlignedDPRCS2Spills()
1846         .addReg(ARM::R4)  in emitAlignedDPRCS2Spills()
1852   std::prev(MI)->addRegisterKilled(ARM::R4, TRI);  in emitAlignedDPRCS2Spills()
1879     assert(MI->killsRegister(ARM::R4, /*TRI=*/nullptr) && "Missed kill flag");  in skipAlignedDPRCS2Spills()
1915   BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)  in emitAlignedDPRCS2Restores()
1929         .addReg(ARM::R4, RegState::Define)  in emitAlignedDPRCS2Restores()
1930         .addReg(ARM::R4, RegState::Kill)  in emitAlignedDPRCS2Restores()
1947         .addReg(ARM::R4)  in emitAlignedDPRCS2Restores()
1960         .addReg(ARM::R4)  in emitAlignedDPRCS2Restores()
1970         .addReg(ARM::R4)  in emitAlignedDPRCS2Restores()
1975   std::prev(MI)->addRegisterKilled(ARM::R4, TRI);  in emitAlignedDPRCS2Restores()
2215   SavedRegs.set(ARM::R4);  in checkNumAlignedDPRCS2Regs()
2298     SavedRegs.set(ARM::R4);  in determineCalleeSaves()
2307     SavedRegs.set(ARM::R4);  in determineCalleeSaves()
2324       SavedRegs.set(ARM::R4);  in determineCalleeSaves()
2382       case ARM::R4: case ARM::R5:  in determineCalleeSaves()
2398       case ARM::R4: case ARM::R5:  in determineCalleeSaves()
2592       for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {  in determineCalleeSaves()
3011   unsigned ScratchReg0 = ARM::R4;  in adjustForSegmentedStacks()