Lines Matching refs:Some

245 // Some targets (e.g. Swift) have microcoded VGETLNi32.
251 // Some targets (e.g. Swift) have microcoded VDUP32.
257 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
269 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
283 // Some targets have a renaming dependency when loading into D subregisters.
294 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
300 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
314 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
319 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
327 // Some processors benefit from using NEON instructions for scalar
343 // Some processors have a nonpipelined VFP coprocessor.
349 // Some processors have FP multiply-accumulate instructions that don't
387 /// Some instructions update CPSR partially, which can add false dependency for
412 // Some processors perform return stack prediction. CodeGen should avoid issue
418 // Some processors have no branch predictor, which changes the expected cost of