Lines Matching +full:non +full:- +full:muxed
1 //===----------------------------------------------------------------------===//
6 def ModeThumb : SubtargetFeature<"thumb-mode", "IsThumb",
10 def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",
14 //===----------------------------------------------------------------------===//
21 string TargetFeatureName, // String used for -target-feature.
32 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
38 // extension) and MVE (even in the integer-only version).
40 "Enable 16-bit FP registers",
44 "Enable 64-bit FP registers",
58 /// 16 d-registers, or both.
65 description#" with only 16 d-registers and no double precision",
76 description#" with only 16 d-registers",
103 // True if subtarget supports half-precision FP conversions.
105 "Enable half-precision "
111 defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
114 // True if subtarget supports half-precision FP operations.
116 "Enable full half-precision "
120 // True if subtarget supports half-precision FP fml operations.
122 "Enable full half-precision "
132 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
151 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
158 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "IsFPBrccSlow", "true",
162 // include a generic cycle-counter as well as more fine-grained (often
163 // implementation-specific) events.
176 // True if processor supports ARMv8-M Security Extensions.
178 "Enable support for ARMv8-M "
209 // Fast computation of non-negative address offsets.
217 def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
222 def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
226 def FeatureReadTpTPIDRURW : SubtargetFeature<"read-tp-tpidrurw", "IsReadTPTPIDRURW", "true",
228 def FeatureReadTpTPIDRURO : SubtargetFeature<"read-tp-tpidruro", "IsReadTPTPIDRURO", "true",
230 def FeatureReadTpTPIDRPRW : SubtargetFeature<"read-tp-tpidrprw", "IsReadTPTPIDRPRW", "true",
237 "Has zero-cycle zeroing instructions">;
239 // Whether it is profitable to unpredicate certain instructions during if-conversion.
241 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
247 def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
249 "Has slow VGETLNi32 - prefer VMOV">;
253 def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
255 "Has slow VDUP32 - prefer VMOV">;
257 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
260 def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
266 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHSTBarriers",
269 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
271 def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits",
273 "Has muxed AGU and NEON/FPU">;
279 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "HasSlowOddRegister",
285 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
290 def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp",
294 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
296 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
300 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
303 def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
310 def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx",
316 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
319 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
322 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs",
328 // single-precision FP operations. This affects instruction selection and should
339 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAccessAlignment",
345 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
349 // Some processors have FP multiply-accumulate instructions that don't
363 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
366 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
370 // Disable 32-bit to 16-bit narrowing for experimentation.
371 // True if codegen would prefer 32-bit Thumb instructions over 16-bit ones.
373 "Prefer 32-bit Thumb instrs">;
375 def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2",
376 "Prefer 32-bit alignment for loops">;
388 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
394 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
399 /// Enabled for Cortex-A57.
400 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
401 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
407 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
414 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
424 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
438 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
447 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
453 def FeatureStrictAlign : SubtargetFeature<"strict-align",
459 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
464 def FeatureExecuteOnly : SubtargetFeature<"execute-only",
470 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
475 // 32-bit imms (including global addresses).
476 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
478 "32-bit imms">;
481 /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
483 : SubtargetFeature<"no-neg-immediates",
491 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
495 def FeatureUseMIPipeliner: SubtargetFeature<"use-mipipeliner", "UseMIPipeliner", "true",
499 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
503 // Armv8.5-A extensions
509 // Armv8.6-A extensions
515 // True if subtarget supports 8-bit integer matrix multiply.
519 // Armv8.1-M extensions
526 // Mitigate against the cve-2021-35465 security vulnurability.
527 def FeatureFixCMSE_CVE_2021_35465 : SubtargetFeature<"fix-cmse-cve-2021-35465",
529 "Mitigate against the cve-2021-35465 "
536 /// Don't place a BTI instruction after return-twice constructs (setjmp).
537 def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
540 "after a return-twice">;
542 // Armv8.9-A/Armv9.4-A 2022 Architecture Extensions
547 def FeatureFixCortexA57AES1742098 : SubtargetFeature<"fix-cortex-a57-aes-1742098",
549 "Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)">;
553 // the frame pointer for Thumb1-only code, which is more efficient, but less
555 // are emitted, that is controlled by the "frame-pointer" function attribute.
556 def FeatureAAPCSFrameChain : SubtargetFeature<"aapcs-frame-chain",
560 // Assume that lock-free 32-bit atomics are available, even if the target
563 // built with this feature is not ABI-compatible with code built without this
566 "atomics-32", "HasForced32BitAtomics", "true",
567 "Assume that lock-free 32-bit atomics are available">;
569 //===----------------------------------------------------------------------===//
573 // A-series ISA
577 // R-series ISA
581 // M-series ISA
593 //===----------------------------------------------------------------------===//
700 // Armv9.5-A is a v9-only architecture. From v9.5-A onwards there's no mapping
708 "Support ARM v8-1M Mainline instructions",
712 "Support M-Class Vector Extension with integer ops",
716 "Support M-Class Vector Extension with integer and floating ops",
723 foreach i = {0-7} in
729 //===----------------------------------------------------------------------===//
731 //===----------------------------------------------------------------------===//
734 def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
739 def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
743 def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",
747 //===----------------------------------------------------------------------===//
750 // In the current Arm architecture, this is usually little-endian regardless of
752 // to match data endianness, so that a big-endian system was consistently big-
753 // endian. And Armv7-R can be configured to use big-endian instructions.
755 // Additionally, even when targeting Armv7-A, big-endian instructions can be
757 // linker byte-reverses them depending on the target architecture.
759 // So we have a feature here to indicate that instructions are stored big-
761 def ModeBigEndianInstructions : SubtargetFeature<"big-endian-instructions",
763 "Expect instructions to be stored big-endian.">;