Lines Matching full:true
5 // True if compiling for Thumb, false for ARM.
7 "true", "Thumb mode">;
9 // True if we're using software floating point features.
11 "true", "Use software floating "
25 > : SubtargetFeature<TargetFeatureName, "Has" # Spelling, "true", Desc, Implies>
34 def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true",
39 def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true",
43 def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true",
47 // True if the floating point unit supports double precision.
48 def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true",
53 // True if subtarget has the full 32 double precision FP registers for VFPv3.
54 def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true",
64 name#"d16sp", query#"D16SP", "true",
70 name#"sp", query#"SP", "true",
75 name#"d16", query#"D16", "true",
81 name, query, "true", description,
87 def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
92 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
99 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
103 // True if subtarget supports half-precision FP conversions.
104 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
114 // True if subtarget supports half-precision FP operations.
115 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
120 // True if subtarget supports half-precision FP fml operations.
121 def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
126 // True if subtarget supports [su]div in Thumb mode.
128 "HasDivideInThumbMode", "true",
131 // True if subtarget supports [su]div in ARM mode.
133 "HasDivideInARMMode", "true",
138 // True if the subtarget supports DMB / DSB data barrier instructions.
139 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
142 // True if the subtarget supports CLREX instructions.
143 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
146 // True if the subtarget supports DFB data barrier instruction.
147 def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
150 // True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
152 "HasAcquireRelease", "true",
157 // True if floating point compare + branch is slow.
158 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "IsFPBrccSlow", "true",
161 // True if the processor supports the Performance Monitor Extensions. These
164 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
171 // True if processor supports TrustZone security extensions.
172 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
176 // True if processor supports ARMv8-M Security Extensions.
177 def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
181 // True if processor supports SHA1 and SHA256.
182 def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true",
185 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
188 // True if processor supports Cryptography extensions.
189 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
194 // True if processor supports CRC instructions.
195 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
198 // True if the ARMv8.2A dot product instructions are supported.
199 def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true",
203 // True if the processor supports RAS extensions.
205 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
210 // True if processor does positive address offset computation faster.
211 def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
216 // True if processor executes back to back AES instruction pairs faster.
217 def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
221 // True if processor executes back to back bottom and top halves of literal generation faster.
222 def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
226 def FeatureReadTpTPIDRURW : SubtargetFeature<"read-tp-tpidrurw", "IsReadTPTPIDRURW", "true",
228 def FeatureReadTpTPIDRURO : SubtargetFeature<"read-tp-tpidruro", "IsReadTPTPIDRURO", "true",
230 def FeatureReadTpTPIDRPRW : SubtargetFeature<"read-tp-tpidrprw", "IsReadTPTPIDRPRW", "true",
234 // True if the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
236 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
240 // True if if conversion may decide to leave some instructions unpredicated.
242 "IsProfitableToUnpredicate", "true",
246 // True if VMOV will be favored over VGETLNi32.
248 "HasSlowVGETLNi32", "true",
252 // True if VMOV will be favored over VDUP.
254 "true",
259 // True if VMOVSR will be favored over VMOVDRR.
261 "true", "Prefer VMOVSR">;
265 // True if ISHST barriers will be used for Release semantics.
267 "true", "Prefer ISHST barriers">;
270 // True if the AGU and NEON/FPU units are multiplexed.
272 "true",
277 // True if a VLDM/VSTM starting with an odd register number is considered to
280 "true", "VLDM/VSTM starting "
284 // True if loading into a D subregister will be penalized.
286 "HasSlowLoadDSubregister", "true",
289 // True if use a wider stride when allocating VFP registers.
291 "UseWideStrideVFP", "true",
295 // True if VMOVS will never be widened to VMOVD.
297 "DontWidenVMOVS", "true",
302 // True if splat a register between VFP and NEON instructions.
304 "UseSplatVFPToNeon", "true",
309 // True if run the MLx expansion pass.
311 "ExpandMLx", "true",
315 // True if VFP/NEON VMLA/VMLS have special RAW hazards.
317 "true", "Has VMLx hazards">;
321 // True if VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
323 "UseNEONForFPMovs", "true",
333 "true",
338 // True if VLDn instructions take an extra cycle for unaligned accesses.
340 "true",
344 // True if VFP instructions are not pipelined.
346 "NonpipelinedVFP", "true",
354 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
360 def FeatureHasSlowFPVFMx : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true",
364 /// True if NEON has special multiplier accumulator
367 "HasVMLxForwarding", "true",
371 // True if codegen would prefer 32-bit Thumb instructions over 16-bit ones.
372 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Prefers32BitThumb", "true",
391 /// True if codegen would avoid using instructions
395 "AvoidCPSRPartialUpdate", "true",
400 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
403 "true",
406 // True if codegen should avoid using flag setting movs with shifter operand (i.e. asr, lsl, lsr).
408 "AvoidMOVsShifterOperand", "true",
415 "HasRetAddrStack", "true",
421 // True if the subtarget has a branch predictor. Having
429 /// True if the subtarget supports the DSP (saturating arith and such) instructions.
430 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
434 // True if the subtarget supports Multiprocessing extension (ARMv7 only).
435 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
440 "HasVirtualization", "true",
446 // True if NaCl TRAP instruction is generated instead of the regular TRAP.
447 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
450 // True if the subtarget disallows unaligned memory
454 "StrictAlign", "true",
459 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
465 "GenExecuteOnly", "true",
469 // True if R9 is not available as a general purpose register.
470 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
474 // True if MOVT / MOVW pairs are not used for materialization of
476 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
491 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
495 def FeatureUseMIPipeliner: SubtargetFeature<"use-mipipeliner", "UseMIPipeliner", "true",
500 "DisablePostRAScheduler", "true",
506 def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",
511 // True if subtarget supports BFloat16 floating point operations.
512 def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", "true",
515 // True if subtarget supports 8-bit integer matrix multiply.
517 "true", "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>;
521 // True if the processor supports the Low Overhead Branch extension.
522 def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true",
528 "FixCMSE_CVE_2021_35465", "true",
532 def FeaturePACBTI : SubtargetFeature<"pacbti", "HasPACBTI", "true",
538 "NoBTIAtReturnTwice", "true",
543 def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", "true",
548 "FixCortexA57AES1742098", "true",
557 "CreateAAPCSFrameChain", "true",
566 "atomics-32", "HasForced32BitAtomics", "true",
585 // True if Thumb2 instructions are supported.
586 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
589 // True if subtarget does not support ARM mode execution.
590 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
598 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
601 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
605 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
610 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
614 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
618 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
622 def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
626 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
630 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
635 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
639 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
643 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
647 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
651 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
655 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
659 def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
663 def HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true",
668 def HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true",
672 def HasV8_8aOps : SubtargetFeature<"v8.8a", "HasV8_8aOps", "true",
676 def HasV8_9aOps : SubtargetFeature<"v8.9a", "HasV8_9aOps", "true",
680 def HasV9_0aOps : SubtargetFeature<"v9a", "HasV9_0aOps", "true",
684 def HasV9_1aOps : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true",
688 def HasV9_2aOps : SubtargetFeature<"v9.2a", "HasV9_2aOps", "true",
692 def HasV9_3aOps : SubtargetFeature<"v9.3a", "HasV9_3aOps", "true",
696 def HasV9_4aOps : SubtargetFeature<"v9.4a", "HasV9_4aOps", "true",
702 def HasV9_5aOps : SubtargetFeature<"v9.5a", "HasV9_5aOps", "true",
707 "v8.1m.main", "HasV8_1MMainlineOps", "true",
711 "mve", "HasMVEIntegerOps", "true",
715 "mve.fp", "HasMVEFloatOps", "true",
719 def HasCDEOps : SubtargetFeature<"cde", "HasCDEOps", "true",
725 "CoprocCDE["#i#"]", "true",
735 "HardenSlsRetBr", "true",
740 "HardenSlsBlr", "true",
744 "HardenSlsNoComdat", "true",
762 "BigEndianInstructions", "true",