1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
9 // This file contains the code shared between ARM CodeGen and ARM MC
28   case ARM::tADC:  in isV8EligibleForIT()
29   case ARM::tADDi3:  in isV8EligibleForIT()
30   case ARM::tADDi8:  in isV8EligibleForIT()
31   case ARM::tADDrr:  in isV8EligibleForIT()
32   case ARM::tAND:  in isV8EligibleForIT()
33   case ARM::tASRri:  in isV8EligibleForIT()
34   case ARM::tASRrr:  in isV8EligibleForIT()
35   case ARM::tBIC:  in isV8EligibleForIT()
36   case ARM::tEOR:  in isV8EligibleForIT()
37   case ARM::tLSLri:  in isV8EligibleForIT()
38   case ARM::tLSLrr:  in isV8EligibleForIT()
39   case ARM::tLSRri:  in isV8EligibleForIT()
40   case ARM::tLSRrr:  in isV8EligibleForIT()
41   case ARM::tMOVi8:  in isV8EligibleForIT()
42   case ARM::tMUL:  in isV8EligibleForIT()
43   case ARM::tMVN:  in isV8EligibleForIT()
44   case ARM::tORR:  in isV8EligibleForIT()
45   case ARM::tROR:  in isV8EligibleForIT()
46   case ARM::tRSB:  in isV8EligibleForIT()
47   case ARM::tSBC:  in isV8EligibleForIT()
48   case ARM::tSUBi3:  in isV8EligibleForIT()
49   case ARM::tSUBi8:  in isV8EligibleForIT()
50   case ARM::tSUBrr:  in isV8EligibleForIT()
53   case ARM::tADDrSPi:  in isV8EligibleForIT()
54   case ARM::tCMNz:  in isV8EligibleForIT()
55   case ARM::tCMPi8:  in isV8EligibleForIT()
56   case ARM::tCMPr:  in isV8EligibleForIT()
57   case ARM::tLDRBi:  in isV8EligibleForIT()
58   case ARM::tLDRBr:  in isV8EligibleForIT()
59   case ARM::tLDRHi:  in isV8EligibleForIT()
60   case ARM::tLDRHr:  in isV8EligibleForIT()
61   case ARM::tLDRSB:  in isV8EligibleForIT()
62   case ARM::tLDRSH:  in isV8EligibleForIT()
63   case ARM::tLDRi:  in isV8EligibleForIT()
64   case ARM::tLDRr:  in isV8EligibleForIT()
65   case ARM::tLDRspi:  in isV8EligibleForIT()
66   case ARM::tSTRBi:  in isV8EligibleForIT()
67   case ARM::tSTRBr:  in isV8EligibleForIT()
68   case ARM::tSTRHi:  in isV8EligibleForIT()
69   case ARM::tSTRHr:  in isV8EligibleForIT()
70   case ARM::tSTRi:  in isV8EligibleForIT()
71   case ARM::tSTRr:  in isV8EligibleForIT()
72   case ARM::tSTRspi:  in isV8EligibleForIT()
73   case ARM::tTST:  in isV8EligibleForIT()
76   case ARM::tADDspr:  in isV8EligibleForIT()
77   case ARM::tBLXr:  in isV8EligibleForIT()
78   case ARM::tBLXr_noip:  in isV8EligibleForIT()
79     return Instr->getOperand(2).getReg() != ARM::PC;  in isV8EligibleForIT()
82   case ARM::tADDrSP:  in isV8EligibleForIT()
83   case ARM::tBX:  in isV8EligibleForIT()
84     return Instr->getOperand(0).getReg() != ARM::PC;  in isV8EligibleForIT()
85   case ARM::tADDhirr:  in isV8EligibleForIT()
86     return Instr->getOperand(0).getReg() != ARM::PC &&  in isV8EligibleForIT()
87            Instr->getOperand(2).getReg() != ARM::PC;  in isV8EligibleForIT()
88   case ARM::tCMPhir:  in isV8EligibleForIT()
89   case ARM::tMOVr:  in isV8EligibleForIT()
90     return Instr->getOperand(0).getReg() != ARM::PC &&  in isV8EligibleForIT()
91            Instr->getOperand(1).getReg() != ARM::PC;  in isV8EligibleForIT()