118   bool isThumb2;  member in __anone34823300111::ARMFastISel
130       isThumb2 = AFI->isThumbFunction();  in ARMFastISel()
461     unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;  in ARMMaterializeInt()
462     const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :  in ARMMaterializeInt()
474     bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :  in ARMMaterializeInt()
477       unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;  in ARMMaterializeInt()
478       const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :  in ARMMaterializeInt()
503   if (isThumb2)  in ARMMaterializeInt()
531   const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass  in ARMMaterializeGV()
551       Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;  in ARMMaterializeGV()
553       Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;  in ARMMaterializeGV()
573     if (isThumb2) {  in ARMMaterializeGV()
607     if (isThumb2)  in ARMMaterializeGV()
656     unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;  in fastMaterializeAlloca()
812         if (needsLowering && isThumb2)  in ARMSimplifyAddress()
831     const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass  in ARMSimplifyAddress()
834     unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;  in ARMSimplifyAddress()
910       if (isThumb2) {  in ARMEmitLoad()
923       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;  in ARMEmitLoad()
930       if (isThumb2) {  in ARMEmitLoad()
939       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;  in ARMEmitLoad()
946       if (isThumb2) {  in ARMEmitLoad()
954       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;  in ARMEmitLoad()
962         Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;  in ARMEmitLoad()
963         RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;  in ARMEmitLoad()
1048       Register Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass  in ARMEmitStore()
1050       unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;  in ARMEmitStore()
1059       if (isThumb2) {  in ARMEmitStore()
1073       if (isThumb2) {  in ARMEmitStore()
1088       if (isThumb2) {  in ARMEmitStore()
1107         StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;  in ARMEmitStore()
1252       unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;  in SelectBranch()
1262       unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;  in SelectBranch()
1275       unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;  in SelectBranch()
1300   unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;  in SelectBranch()
1313   unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;  in SelectBranch()
1324   unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;  in SelectIndirectBr()
1325   assert(isThumb2 || Subtarget->hasV4TOps());  in SelectIndirectBr()
1369       UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :  in ARMEmitCmp()
1398       if (isThumb2) {  in ARMEmitCmp()
1471   unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;  in SelectCmp()
1472   const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass  in SelectCmp()
1626     UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :  in SelectSelect()
1636   unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;  in SelectSelect()
1646     RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;  in SelectSelect()
1647     MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;  in SelectSelect()
1649     RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;  in SelectSelect()
1651       MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;  in SelectSelect()
1653       MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;  in SelectSelect()
1748       Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;  in SelectBinaryIntOp()
1751       Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;  in SelectBinaryIntOp()
1754       Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;  in SelectBinaryIntOp()
2159     if (isThumb2)  in SelectRet()
2176     return isThumb2 ? gettBLXrOpcode(*MF) : getBLXOpcode(*MF);  in ARMSelectCallOp()
2178     return isThumb2 ? ARM::tBL : ARM::BL;  in ARMSelectCallOp()
2266   if (isThumb2)  in ARMEmitLibcall()
2270         constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0);  in ARMEmitLibcall()
2408   if(isThumb2)  in SelectCall()
2412         constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0);  in SelectCall()
2494     unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;  in SelectIntrinsicCall()
2495     const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass  in SelectIntrinsicCall()
2692   bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];  in ARMEmitIntExt()
2693   const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];  in ARMEmitIntExt()
2694   const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];  in ARMEmitIntExt()
2705   unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;  in ARMEmitIntExt()
2774   if (isThumb2)  in SelectShift()
2934     if (FLE.Opc[isThumb2] == MI->getOpcode() &&  in tryToFoldLoadIntoMI()
2973   unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;  in ARMLowerPICELF()