Lines Matching refs:RegSpc
518 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, in GetDSubRegs() argument
521 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) { in GetDSubRegs()
526 } else if (RegSpc == SingleHighQSpc) { in GetDSubRegs()
531 } else if (RegSpc == SingleHighTSpc) { in GetDSubRegs()
536 } else if (RegSpc == EvenDblSpc) { in GetDSubRegs()
542 assert(RegSpc == OddDblSpc && "unknown register spacing"); in GetDSubRegs()
559 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandVLD() local
581 if (RegSpc == EvenDblSpc) { in ExpandVLD()
584 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); in ExpandVLD()
593 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandVLD()
643 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || in ExpandVLD()
644 RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc) in ExpandVLD()
677 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandVST() local
719 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandVST()
753 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandLaneOp() local
765 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); in ExpandLaneOp()
766 if (RegSpc == EvenDblSpc && Lane >= RegElts) { in ExpandLaneOp()
767 RegSpc = OddDblSpc; in ExpandLaneOp()
778 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandLaneOp()
801 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); in ExpandLaneOp()