566   bool DstIsDead = MI.getOperand(OpIdx).isDead();  in ExpandVLD()  local
590     MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
594     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
596       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
598       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
600       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
659   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandVLD()
774   bool DstIsDead = false;  in ExpandLaneOp()  local
776     DstIsDead = MI.getOperand(OpIdx).isDead();  in ExpandLaneOp()
779     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
781       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
783       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
785       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
827     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandLaneOp()
997   bool DstIsDead = MI.getOperand(0).isDead();  in ExpandTMOV32BitImm()  local
1054   (--MBBI)->getOperand(0).setIsDead(DstIsDead);  in ExpandTMOV32BitImm()
1066   bool DstIsDead = MI.getOperand(0).isDead();  in ExpandMOV32BitImm()  local
1085           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1092           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1140                .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1149     LO16->getOperand(0).setIsDead(DstIsDead);  in ExpandMOV32BitImm()
2622       bool DstIsDead = MI.getOperand(0).isDead();  in ExpandMI()  local
2629           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2644       bool DstIsDead = MI.getOperand(0).isDead();  in ExpandMI()  local
2688             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2705       bool DstIsDead = MI.getOperand(0).isDead();  in ExpandMI()  local
2730         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2782       bool DstIsDead = MI.getOperand(OpIdx).isDead();  in ExpandMI()  local
2795       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2796         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandMI()
2799       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandMI()