519                         const TargetRegisterInfo *TRI, unsigned &D0,  in GetDSubRegs()  argument
522     D0 = TRI->getSubReg(Reg, ARM::dsub_0);  in GetDSubRegs()
527     D0 = TRI->getSubReg(Reg, ARM::dsub_4);  in GetDSubRegs()
532     D0 = TRI->getSubReg(Reg, ARM::dsub_3);  in GetDSubRegs()
537     D0 = TRI->getSubReg(Reg, ARM::dsub_0);  in GetDSubRegs()
543     D0 = TRI->getSubReg(Reg, ARM::dsub_1);  in GetDSubRegs()
592     unsigned D0, D1, D2, D3;  in ExpandVLD()  local
593     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);  in ExpandVLD()
594     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
718   unsigned D0, D1, D2, D3;  in ExpandVST()  local
719   GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);  in ExpandVST()
720   MIB.addReg(D0, getUndefRegState(SrcIsUndef));  in ExpandVST()
772   unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;  in ExpandLaneOp()  local
778     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);  in ExpandLaneOp()
779     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
801     GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);  in ExpandLaneOp()
806   MIB.addReg(D0, SrcFlags);  in ExpandLaneOp()
854   unsigned D0, D1, D2, D3;  in ExpandVTBL()  local
855   GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);  in ExpandVTBL()
856   MIB.addReg(D0);  in ExpandVTBL()
1222           (Reg >= ARM::D0 && Reg <= ARM::D15) ||  in determineFPRegsToClear()
1231     } else if (Reg >= ARM::D0 && Reg <= ARM::D15) {  in determineFPRegsToClear()
1232       int R = Reg - ARM::D0;  in determineFPRegsToClear()
1320       unsigned Reg = ARM::D0 + D;  in CMSEClearFPRegsV8()
1507             .addImm((Reg - ARM::D0) * 2)  in CMSESaveClearFPRegsV8()
1515             .addImm((Reg - ARM::D0) * 2)  in CMSESaveClearFPRegsV8()
1519             .addImm((Reg - ARM::D0) * 2 + 1)  in CMSESaveClearFPRegsV8()
1676           .addImm((Reg - ARM::D0) * 2)  in CMSERestoreFPRegsV8()
1755         (Reg >= ARM::D0 && Reg <= ARM::D15) ||  in definesOrUsesFPReg()
2793       Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0);  in ExpandMI()  local
2795       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2825       Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);  in ExpandMI()  local
2827       MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)  in ExpandMI()