Lines Matching +full:reg +full:- +full:spacing
1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // instructions to allow proper scheduling, if-conversion, and other late
12 // the post-regalloc scheduling pass.
14 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "arm-pseudo"
35 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
125 // Constants for register spacing in NEON load/store instructions.
126 // For quad-register load-lane and store-lane pseudo instructors, the
127 // spacing is initially assumed to be EvenDblSpc, and that is changed to
131 SingleLowSpc , // Single spacing, low registers, three and four vectors.
132 SingleHighQSpc, // Single spacing, high registers, four vectors.
133 SingleHighTSpc, // Single spacing, high registers, three vectors.
139 // PseudoOpc for fast binary-search lookups.
497 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
510 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) in LookupNEONLdSt()
515 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
516 /// corresponding to the specified register spacing. Not all of the results
518 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, in GetDSubRegs() argument
522 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
523 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
524 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
525 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
527 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
528 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
529 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
530 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
532 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
533 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
534 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
535 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
537 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
538 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
539 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
540 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
542 assert(RegSpc == OddDblSpc && "unknown register spacing"); in GetDSubRegs()
543 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
544 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
545 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
546 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
550 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
558 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); in ExpandVLD()
559 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandVLD()
560 unsigned NumRegs = TableEntry->NumRegs; in ExpandVLD()
563 TII->get(TableEntry->RealOpc)); in ExpandVLD()
569 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 || in ExpandVLD()
570 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || in ExpandVLD()
571 TableEntry->RealOpc == ARM::VLD2DUPd32x2 || in ExpandVLD()
572 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed || in ExpandVLD()
573 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed || in ExpandVLD()
574 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed || in ExpandVLD()
575 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register || in ExpandVLD()
576 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register || in ExpandVLD()
577 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register; in ExpandVLD()
584 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); in ExpandVLD()
587 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex); in ExpandVLD()
588 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, in ExpandVLD()
595 if (NumRegs > 1 && TableEntry->copyAllListRegs) in ExpandVLD()
597 if (NumRegs > 2 && TableEntry->copyAllListRegs) in ExpandVLD()
599 if (NumRegs > 3 && TableEntry->copyAllListRegs) in ExpandVLD()
603 if (TableEntry->isUpdating) in ExpandVLD()
611 if (TableEntry->hasWritebackOperand) { in ExpandVLD()
612 // TODO: The writing-back pseudo instructions we translate here are all in ExpandVLD()
617 // such instructions. Once all real and pseudo writing-back instructions are in ExpandVLD()
620 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || in ExpandVLD()
621 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || in ExpandVLD()
622 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || in ExpandVLD()
623 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || in ExpandVLD()
624 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || in ExpandVLD()
625 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || in ExpandVLD()
626 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || in ExpandVLD()
627 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed || in ExpandVLD()
628 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed || in ExpandVLD()
629 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed || in ExpandVLD()
630 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) { in ExpandVLD()
632 "A fixed writing-back pseudo instruction provides an offset " in ExpandVLD()
639 // For an instruction writing double-spaced subregs, the pseudo instruction in ExpandVLD()
640 // has an extra operand that is a use of the super-register. Record the in ExpandVLD()
651 // Copy the super-register source operand used for double-spaced subregs over in ExpandVLD()
658 // Add an implicit def for the super-register. in ExpandVLD()
665 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); in ExpandVLD()
668 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
676 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); in ExpandVST()
677 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandVST()
678 unsigned NumRegs = TableEntry->NumRegs; in ExpandVST()
681 TII->get(TableEntry->RealOpc)); in ExpandVST()
683 if (TableEntry->isUpdating) in ExpandVST()
690 if (TableEntry->hasWritebackOperand) { in ExpandVST()
691 // TODO: The writing-back pseudo instructions we translate here are all in ExpandVST()
696 // such instructions. Once all real and pseudo writing-back instructions are in ExpandVST()
699 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || in ExpandVST()
700 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || in ExpandVST()
701 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || in ExpandVST()
702 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || in ExpandVST()
703 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || in ExpandVST()
704 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || in ExpandVST()
705 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || in ExpandVST()
706 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { in ExpandVST()
708 "A fixed writing-back pseudo instruction provides an offset " in ExpandVST()
721 if (NumRegs > 1 && TableEntry->copyAllListRegs) in ExpandVST()
723 if (NumRegs > 2 && TableEntry->copyAllListRegs) in ExpandVST()
725 if (NumRegs > 3 && TableEntry->copyAllListRegs) in ExpandVST()
732 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. in ExpandVST()
733 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandVST()
735 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
741 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); in ExpandVST()
744 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
753 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandLaneOp()
754 unsigned NumRegs = TableEntry->NumRegs; in ExpandLaneOp()
755 unsigned RegElts = TableEntry->RegElts; in ExpandLaneOp()
758 TII->get(TableEntry->RealOpc)); in ExpandLaneOp()
762 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); in ExpandLaneOp()
764 // Adjust the lane and spacing as needed for Q registers. in ExpandLaneOp()
765 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); in ExpandLaneOp()
768 Lane -= RegElts; in ExpandLaneOp()
770 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); in ExpandLaneOp()
775 if (TableEntry->IsLoad) { in ExpandLaneOp()
788 if (TableEntry->isUpdating) in ExpandLaneOp()
795 if (TableEntry->hasWritebackOperand) in ExpandLaneOp()
798 // Grab the super-register source. in ExpandLaneOp()
800 if (!TableEntry->IsLoad) in ExpandLaneOp()
822 // Copy the super-register source to be an implicit source. in ExpandLaneOp()
825 if (TableEntry->IsLoad) in ExpandLaneOp()
826 // Add an implicit def for the super-register. in ExpandLaneOp()
834 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
842 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL()
866 // Add an implicit kill and use for the super-reg. in ExpandVTBL()
870 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); in ExpandVTBL()
881 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMQQPRLoadStore()
890 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags); in ExpandMQQPRLoadStore()
891 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags); in ExpandMQQPRLoadStore()
892 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags); in ExpandMQQPRLoadStore()
893 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags); in ExpandMQQPRLoadStore()
896 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags); in ExpandMQQPRLoadStore()
897 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags); in ExpandMQQPRLoadStore()
898 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags); in ExpandMQQPRLoadStore()
899 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags); in ExpandMQQPRLoadStore()
943 llvm_unreachable("should not exist post-isel"); in IsAnAddressOperand()
1022 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg) in ExpandTMOV32BitImm()
1029 LLVM_DEBUG(dbgs() << "And: "; Lsl->dump();); in ExpandTMOV32BitImm()
1036 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Op), DstReg) in ExpandTMOV32BitImm()
1044 MIB.getInstr()->dump();); in ExpandTMOV32BitImm()
1054 (--MBBI)->getOperand(0).setIsDead(DstIsDead); in ExpandTMOV32BitImm()
1069 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); in ExpandMOV32BitImm()
1073 if (!STI->hasV6T2Ops() && in ExpandMOV32BitImm()
1076 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); in ExpandMOV32BitImm()
1078 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); in ExpandMOV32BitImm()
1083 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
1084 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
1090 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
1091 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri)) in ExpandMOV32BitImm()
1094 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(-ImmVal); in ExpandMOV32BitImm()
1095 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(-ImmVal); in ExpandMOV32BitImm()
1096 SOImmValV1 = ~(-SOImmValV1); in ExpandMOV32BitImm()
1127 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); in ExpandMOV32BitImm()
1135 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump();); in ExpandMOV32BitImm()
1139 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) in ExpandMOV32BitImm()
1147 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump();); in ExpandMOV32BitImm()
1149 LO16->getOperand(0).setIsDead(DstIsDead); in ExpandMOV32BitImm()
1153 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); in ExpandMOV32BitImm()
1159 // S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad)
1182 if (STI->hasV8_1MMainlineOps()) { in CMSEClearGPRegs()
1185 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL)); in CMSEClearGPRegs()
1193 for (unsigned Reg : ClearRegs) { in CMSEClearGPRegs() local
1194 if (Reg == ClobberReg) in CMSEClearGPRegs()
1196 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg) in CMSEClearGPRegs()
1201 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M)) in CMSEClearGPRegs()
1202 .addImm(STI->hasDSP() ? 0xc00 : 0x800) in CMSEClearGPRegs()
1219 Register Reg = Op.getReg(); in determineFPRegsToClear() local
1221 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || in determineFPRegsToClear()
1222 (Reg >= ARM::D0 && Reg <= ARM::D15) || in determineFPRegsToClear()
1223 (Reg >= ARM::S0 && Reg <= ARM::S31)) in determineFPRegsToClear()
1228 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) { in determineFPRegsToClear()
1229 int R = Reg - ARM::Q0; in determineFPRegsToClear()
1231 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) { in determineFPRegsToClear()
1232 int R = Reg - ARM::D0; in determineFPRegsToClear()
1234 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) { in determineFPRegsToClear()
1235 ClearRegs[Reg - ARM::S0] = false; in determineFPRegsToClear()
1247 if (STI->hasV8_1MMainlineOps()) in CMSEClearFPRegs()
1253 // Clear the FP registers for v8.0-M, by copying over the content
1259 if (!STI->hasFPRegs()) in CMSEClearFPRegsV8()
1266 // Otherwise, check the CONTROL.SFPA (Secure Floating-Point Active) bit and in CMSEClearFPRegsV8()
1267 // don't clear them if they belong to the non-secure state. in CMSEClearFPRegsV8()
1269 if (STI->hasMinSize()) { in CMSEClearFPRegsV8()
1273 ClearBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); in CMSEClearFPRegsV8()
1274 DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); in CMSEClearFPRegsV8()
1276 MF->insert(++MBB.getIterator(), ClearBB); in CMSEClearFPRegsV8()
1277 MF->insert(++ClearBB->getIterator(), DoneBB); in CMSEClearFPRegsV8()
1279 DoneBB->splice(DoneBB->end(), &MBB, MBBI, MBB.end()); in CMSEClearFPRegsV8()
1280 DoneBB->transferSuccessors(&MBB); in CMSEClearFPRegsV8()
1283 ClearBB->addSuccessor(DoneBB); in CMSEClearFPRegsV8()
1285 // At the new basic blocks we need to have live-in the registers, used in CMSEClearFPRegsV8()
1290 Register Reg = Op.getReg(); in CMSEClearFPRegsV8() local
1291 if (Reg == ARM::NoRegister || Reg == ARM::LR) in CMSEClearFPRegsV8()
1293 assert(Reg.isPhysical() && "Unallocated register"); in CMSEClearFPRegsV8()
1294 ClearBB->addLiveIn(Reg); in CMSEClearFPRegsV8()
1295 DoneBB->addLiveIn(Reg); in CMSEClearFPRegsV8()
1297 ClearBB->addLiveIn(ARM::LR); in CMSEClearFPRegsV8()
1298 DoneBB->addLiveIn(ARM::LR); in CMSEClearFPRegsV8()
1301 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) in CMSEClearFPRegsV8()
1305 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri)) in CMSEClearFPRegsV8()
1310 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc)) in CMSEClearFPRegsV8()
1320 unsigned Reg = ARM::D0 + D; in CMSEClearFPRegsV8() local
1321 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) in CMSEClearFPRegsV8()
1328 unsigned Reg = ARM::S0 + D * 2; in CMSEClearFPRegsV8() local
1329 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) in CMSEClearFPRegsV8()
1335 unsigned Reg = ARM::S0 + D * 2 + 1; in CMSEClearFPRegsV8() local
1336 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) in CMSEClearFPRegsV8()
1343 // Clear FPSCR bits 0-4, 7, 28-31 in CMSEClearFPRegsV8()
1345 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) in CMSEClearFPRegsV8()
1347 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1352 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1357 BuildMI(ClearBB, DL, TII->get(ARM::VMSR)) in CMSEClearFPRegsV8()
1371 // each contiguous sequence of S-registers. in CMSEClearFPRegsV81()
1372 int Start = -1, End = -1; in CMSEClearFPRegsV81()
1381 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) in CMSEClearFPRegsV81()
1392 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) in CMSEClearFPRegsV81()
1405 if (STI->hasV8_1MMainlineOps()) in CMSESaveClearFPRegs()
1407 else if (STI->hasV8MMainlineOps()) in CMSESaveClearFPRegs()
1421 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) in CMSESaveClearFPRegsV8()
1429 for (const MachineOperand &Op : MBBI->operands()) { in CMSESaveClearFPRegsV8()
1431 Register Reg = Op.getReg(); in CMSESaveClearFPRegsV8() local
1432 assert(!ARM::DPRRegClass.contains(Reg) || in CMSESaveClearFPRegsV8()
1433 ARM::DPR_VFP2RegClass.contains(Reg)); in CMSESaveClearFPRegsV8()
1434 assert(!ARM::QPRRegClass.contains(Reg)); in CMSESaveClearFPRegsV8()
1435 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1439 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2); in CMSESaveClearFPRegsV8()
1442 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSESaveClearFPRegsV8()
1445 .addReg(Reg) in CMSESaveClearFPRegsV8()
1448 NonclearedFPRegs.push_back(Reg); in CMSESaveClearFPRegsV8()
1450 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1453 ClearedFPRegs.emplace_back(Reg, SaveReg, 0); in CMSESaveClearFPRegsV8()
1456 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) in CMSESaveClearFPRegsV8()
1457 .addReg(Reg) in CMSESaveClearFPRegsV8()
1460 NonclearedFPRegs.push_back(Reg); in CMSESaveClearFPRegsV8()
1469 assert(STI->hasFPRegs() && "Subtarget needs fpregs"); in CMSESaveClearFPRegsV8()
1472 // This executes as NOP in the absence of floating-point support. in CMSESaveClearFPRegsV8()
1474 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) in CMSESaveClearFPRegsV8()
1479 // Mark non-live registers as undef in CMSESaveClearFPRegsV8()
1480 for (MachineOperand &MO : VLSTM->implicit_operands()) { in CMSESaveClearFPRegsV8()
1482 Register Reg = MO.getReg(); in CMSESaveClearFPRegsV8() local
1483 MO.setIsUndef(!LiveRegs.contains(Reg)); in CMSESaveClearFPRegsV8()
1489 unsigned Reg, SaveReg1, SaveReg2; in CMSESaveClearFPRegsV8() local
1490 std::tie(Reg, SaveReg1, SaveReg2) = Regs; in CMSESaveClearFPRegsV8()
1491 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSESaveClearFPRegsV8()
1492 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSESaveClearFPRegsV8()
1496 else if (ARM::SPRRegClass.contains(Reg)) in CMSESaveClearFPRegsV8()
1497 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) in CMSESaveClearFPRegsV8()
1502 for (unsigned Reg : NonclearedFPRegs) { in CMSESaveClearFPRegsV8() local
1503 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1504 if (STI->isLittle()) { in CMSESaveClearFPRegsV8()
1505 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg) in CMSESaveClearFPRegsV8()
1507 .addImm((Reg - ARM::D0) * 2) in CMSESaveClearFPRegsV8()
1510 // For big-endian targets we need to load the two subregisters of Reg in CMSESaveClearFPRegsV8()
1512 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0); in CMSESaveClearFPRegsV8()
1513 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0) in CMSESaveClearFPRegsV8()
1515 .addImm((Reg - ARM::D0) * 2) in CMSESaveClearFPRegsV8()
1517 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1) in CMSESaveClearFPRegsV8()
1519 .addImm((Reg - ARM::D0) * 2 + 1) in CMSESaveClearFPRegsV8()
1522 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1523 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg) in CMSESaveClearFPRegsV8()
1525 .addImm(Reg - ARM::S0) in CMSESaveClearFPRegsV8()
1529 // restore FPSCR from stack and clear bits 0-4, 7, 28-31 in CMSESaveClearFPRegsV8()
1532 BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg) in CMSESaveClearFPRegsV8()
1536 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) in CMSESaveClearFPRegsV8()
1541 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) in CMSESaveClearFPRegsV8()
1546 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR)) in CMSESaveClearFPRegsV8()
1550 // post-ra scheduler to mess with the order, we create a bundle. in CMSESaveClearFPRegsV8()
1551 finalizeBundle(MBB, VLSTM->getIterator(), MBBI->getIterator()); in CMSESaveClearFPRegsV8()
1567 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) in CMSESaveClearFPRegsV81()
1574 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) in CMSESaveClearFPRegsV81()
1579 // Mark non-live registers as undef in CMSESaveClearFPRegsV81()
1580 for (MachineOperand &MO : VLSTM->implicit_operands()) { in CMSESaveClearFPRegsV81()
1582 Register Reg = MO.getReg(); in CMSESaveClearFPRegsV81() local
1583 MO.setIsUndef(!LiveRegs.contains(Reg)); in CMSESaveClearFPRegsV81()
1587 // Push all the callee-saved registers (s16-s31). in CMSESaveClearFPRegsV81()
1589 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP) in CMSESaveClearFPRegsV81()
1592 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSESaveClearFPRegsV81() local
1593 VPUSH.addReg(Reg); in CMSESaveClearFPRegsV81()
1598 // Save floating-point context. in CMSESaveClearFPRegsV81()
1599 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP) in CMSESaveClearFPRegsV81()
1601 .addImm(-8) in CMSESaveClearFPRegsV81()
1610 if (STI->hasV8_1MMainlineOps()) in CMSERestoreFPRegs()
1612 else if (STI->hasV8MMainlineOps()) in CMSERestoreFPRegs()
1622 if (STI->fixCMSE_CVE_2021_35465()) in CMSERestoreFPRegsV8()
1628 for (const MachineOperand &Op : MBBI->operands()) { in CMSERestoreFPRegsV8()
1630 Register Reg = Op.getReg(); in CMSERestoreFPRegsV8() local
1631 assert(!ARM::DPRRegClass.contains(Reg) || in CMSERestoreFPRegsV8()
1632 ARM::DPR_VFP2RegClass.contains(Reg)); in CMSERestoreFPRegsV8()
1633 assert(!ARM::QPRRegClass.contains(Reg)); in CMSERestoreFPRegsV8()
1634 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSERestoreFPRegsV8()
1638 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2); in CMSERestoreFPRegsV8()
1641 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSERestoreFPRegsV8()
1644 .addReg(Reg) in CMSERestoreFPRegsV8()
1647 NonclearedFPRegs.push_back(Reg); in CMSERestoreFPRegsV8()
1649 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSERestoreFPRegsV8()
1652 ClearedFPRegs.emplace_back(Reg, SaveReg, 0); in CMSERestoreFPRegsV8()
1655 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) in CMSERestoreFPRegsV8()
1656 .addReg(Reg) in CMSERestoreFPRegsV8()
1659 NonclearedFPRegs.push_back(Reg); in CMSERestoreFPRegsV8()
1668 assert(STI->hasFPRegs() && "Subtarget needs fpregs"); in CMSERestoreFPRegsV8()
1671 for (unsigned Reg : NonclearedFPRegs) { in CMSERestoreFPRegsV8() local
1672 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1673 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD)) in CMSERestoreFPRegsV8()
1674 .addReg(Reg) in CMSERestoreFPRegsV8()
1676 .addImm((Reg - ARM::D0) * 2) in CMSERestoreFPRegsV8()
1678 else if (ARM::SPRRegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1679 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS)) in CMSERestoreFPRegsV8()
1680 .addReg(Reg) in CMSERestoreFPRegsV8()
1682 .addImm(Reg - ARM::S0) in CMSERestoreFPRegsV8()
1687 // This executes as NOP in the absence of floating-point support. in CMSERestoreFPRegsV8()
1689 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) in CMSERestoreFPRegsV8()
1695 if (STI->fixCMSE_CVE_2021_35465()) { in CMSERestoreFPRegsV8()
1698 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2MRS_M)) in CMSERestoreFPRegsV8()
1703 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2TSTri)) in CMSERestoreFPRegsV8()
1708 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2IT)) in CMSERestoreFPRegsV8()
1715 if (STI->hasFPRegs()) in CMSERestoreFPRegsV8()
1716 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::VMOVS)) in CMSERestoreFPRegsV8()
1721 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::INLINEASM)) in CMSERestoreFPRegsV8()
1729 unsigned Reg, SaveReg1, SaveReg2; in CMSERestoreFPRegsV8() local
1730 std::tie(Reg, SaveReg1, SaveReg2) = Regs; in CMSERestoreFPRegsV8()
1731 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1732 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSERestoreFPRegsV8()
1736 else if (ARM::SPRRegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1737 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) in CMSERestoreFPRegsV8()
1743 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) in CMSERestoreFPRegsV8()
1753 Register Reg = Op.getReg(); in definesOrUsesFPReg() local
1754 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || in definesOrUsesFPReg()
1755 (Reg >= ARM::D0 && Reg <= ARM::D15) || in definesOrUsesFPReg()
1756 (Reg >= ARM::S0 && Reg <= ARM::S31)) in definesOrUsesFPReg()
1766 if (STI->fixCMSE_CVE_2021_35465()) { in CMSERestoreFPRegsV81()
1767 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSCCLRMS)) in CMSERestoreFPRegsV81()
1773 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) in CMSERestoreFPRegsV81()
1780 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) in CMSERestoreFPRegsV81()
1786 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post), in CMSERestoreFPRegsV81()
1792 // Pop all the callee-saved registers (s16-s31). in CMSERestoreFPRegsV81()
1794 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP) in CMSERestoreFPRegsV81()
1797 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSERestoreFPRegsV81() local
1798 VPOP.addReg(Reg, RegState::Define); in CMSERestoreFPRegsV81()
1802 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
1803 /// possible. This only gets used at -O0 so we don't care about efficiency of
1810 bool IsThumb = STI->isThumb(); in ExpandCMP_SWAP()
1811 bool IsThumb1Only = STI->isThumb1Only(); in ExpandCMP_SWAP()
1824 assert(STI->hasV8MBaselineOps() && in ExpandCMP_SWAP()
1827 "ARMv8-M.baseline does not have t2UXTB/t2UXTH"); in ExpandCMP_SWAP()
1833 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); in ExpandCMP_SWAP()
1834 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); in ExpandCMP_SWAP()
1835 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); in ExpandCMP_SWAP()
1837 MF->insert(++MBB.getIterator(), LoadCmpBB); in ExpandCMP_SWAP()
1838 MF->insert(++LoadCmpBB->getIterator(), StoreBB); in ExpandCMP_SWAP()
1839 MF->insert(++StoreBB->getIterator(), DoneBB); in ExpandCMP_SWAP()
1843 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) in ExpandCMP_SWAP()
1856 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); in ExpandCMP_SWAP()
1859 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. in ExpandCMP_SWAP()
1863 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) in ExpandCMP_SWAP()
1868 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) in ExpandCMP_SWAP()
1872 LoadCmpBB->addSuccessor(DoneBB); in ExpandCMP_SWAP()
1873 LoadCmpBB->addSuccessor(StoreBB); in ExpandCMP_SWAP()
1879 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) in ExpandCMP_SWAP()
1883 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. in ExpandCMP_SWAP()
1888 BuildMI(StoreBB, DL, TII->get(CMPri)) in ExpandCMP_SWAP()
1892 BuildMI(StoreBB, DL, TII->get(Bcc)) in ExpandCMP_SWAP()
1896 StoreBB->addSuccessor(LoadCmpBB); in ExpandCMP_SWAP()
1897 StoreBB->addSuccessor(DoneBB); in ExpandCMP_SWAP()
1899 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); in ExpandCMP_SWAP()
1900 DoneBB->transferSuccessors(&MBB); in ExpandCMP_SWAP()
1913 StoreBB->clearLiveIns(); in ExpandCMP_SWAP()
1915 LoadCmpBB->clearLiveIns(); in ExpandCMP_SWAP()
1924 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, in addExclusiveRegPair() argument
1928 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair()
1929 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair()
1933 MIB.addReg(Reg.getReg(), Flags); in addExclusiveRegPair()
1936 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
1940 bool IsThumb = STI->isThumb(); in ExpandCMP_SWAP_64()
1941 assert(!STI->isThumb1Only() && "CMP_SWAP_64 unsupported under Thumb1!"); in ExpandCMP_SWAP_64()
1954 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
1955 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
1956 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()
1957 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
1960 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); in ExpandCMP_SWAP_64()
1961 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); in ExpandCMP_SWAP_64()
1962 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); in ExpandCMP_SWAP_64()
1964 MF->insert(++MBB.getIterator(), LoadCmpBB); in ExpandCMP_SWAP_64()
1965 MF->insert(++LoadCmpBB->getIterator(), StoreBB); in ExpandCMP_SWAP_64()
1966 MF->insert(++StoreBB->getIterator(), DoneBB); in ExpandCMP_SWAP_64()
1975 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); in ExpandCMP_SWAP_64()
1980 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) in ExpandCMP_SWAP_64()
1985 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) in ExpandCMP_SWAP_64()
1991 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) in ExpandCMP_SWAP_64()
1995 LoadCmpBB->addSuccessor(DoneBB); in ExpandCMP_SWAP_64()
1996 LoadCmpBB->addSuccessor(StoreBB); in ExpandCMP_SWAP_64()
2003 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); in ExpandCMP_SWAP_64()
2009 BuildMI(StoreBB, DL, TII->get(CMPri)) in ExpandCMP_SWAP_64()
2013 BuildMI(StoreBB, DL, TII->get(Bcc)) in ExpandCMP_SWAP_64()
2017 StoreBB->addSuccessor(LoadCmpBB); in ExpandCMP_SWAP_64()
2018 StoreBB->addSuccessor(DoneBB); in ExpandCMP_SWAP_64()
2020 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); in ExpandCMP_SWAP_64()
2021 DoneBB->transferSuccessors(&MBB); in ExpandCMP_SWAP_64()
2034 StoreBB->clearLiveIns(); in ExpandCMP_SWAP_64()
2036 LoadCmpBB->clearLiveIns(); in ExpandCMP_SWAP_64()
2046 const DebugLoc &DL = MBBI->getDebugLoc(); in CMSEPushCalleeSaves()
2050 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { in CMSEPushCalleeSaves() local
2052 Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef); in CMSEPushCalleeSaves()
2058 // the values of r9-r11, and then r8. That would leave them ordered in in CMSEPushCalleeSaves()
2060 // FIXME: Could also use any of r0-r3 that are free (including in the in CMSEPushCalleeSaves()
2062 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves()
2068 --HiReg; in CMSEPushCalleeSaves()
2072 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { in CMSEPushCalleeSaves() local
2073 if (Reg == JumpReg) in CMSEPushCalleeSaves()
2075 PushMIB2.addReg(Reg, RegState::Kill); in CMSEPushCalleeSaves()
2095 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) { in CMSEPushCalleeSaves() local
2097 Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef); in CMSEPushCalleeSaves()
2106 const DebugLoc &DL = MBBI->getDebugLoc(); in CMSEPopCalleeSaves()
2125 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) in CMSEPopCalleeSaves() local
2126 PopMIB.addReg(Reg, RegState::Define); in CMSEPopCalleeSaves()
2145 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI()
2155 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI()
2166 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI()
2176 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MoveOpc)) in ExpandMI()
2184 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI()
2203 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd) in ExpandMI()
2204 MBBI--; in ExpandMI()
2205 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret) in ExpandMI()
2206 MBBI--; in ExpandMI()
2207 assert(MBBI->isReturn() && in ExpandMI()
2209 unsigned RetOpcode = MBBI->getOpcode(); in ExpandMI()
2210 DebugLoc dl = MBBI->getDebugLoc(); in ExpandMI()
2212 MBB.getParent()->getSubtarget().getInstrInfo()); in ExpandMI()
2216 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd) in ExpandMI()
2217 MBBI--; in ExpandMI()
2218 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret) in ExpandMI()
2219 MBBI--; in ExpandMI()
2220 MachineOperand &JumpTarget = MBBI->getOperand(0); in ExpandMI()
2225 bool NeedsWinCFI = MF->getTarget().getMCAsmInfo()->usesWindowsCFI() && in ExpandMI()
2226 MF->getFunction().needsUnwindTableEntry(); in ExpandMI()
2228 STI->isThumb() in ExpandMI()
2229 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd in ExpandMI()
2243 if (STI->isThumb()) in ExpandMI()
2248 STI->isThumb() ? ARM::tTAILJMPr in ExpandMI()
2249 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); in ExpandMI()
2256 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i) in ExpandMI()
2257 NewMI->addOperand(MBBI->getOperand(i)); in ExpandMI()
2262 MI.getMF()->moveCallSiteInfo(&MI, &*NewMI); in ExpandMI()
2265 NewMI->setFlag(MachineInstr::NoMerge); in ExpandMI()
2272 // For v8.0-M.Main we need to authenticate LR before clearing FPRs, which in ExpandMI()
2274 if (!STI->hasV8_1MMainlineOps() && AFI->shouldSignReturnAddress()) in ExpandMI()
2275 BuildMI(MBB, MBBI, DebugLoc(), TII->get(ARM::t2AUT)); in ExpandMI()
2279 if (STI->hasV8_1MMainlineOps()) { in ExpandMI()
2280 // Restore the non-secure floating point context. in ExpandMI()
2281 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), in ExpandMI()
2282 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP) in ExpandMI()
2287 if (AFI->shouldSignReturnAddress()) in ExpandMI()
2288 BuildMI(AfterBB, AfterBB.end(), DebugLoc(), TII->get(ARM::t2AUT)); in ExpandMI()
2292 assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) { in ExpandMI()
2298 CMSEClearGPRegs(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), ClearRegs, in ExpandMI()
2302 BuildMI(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), in ExpandMI()
2303 TII->get(ARM::tBXNS)) in ExpandMI()
2307 NewMI->addOperand(Op); in ExpandMI()
2312 DebugLoc DL = MBBI->getDebugLoc(); in ExpandMI()
2313 Register JumpReg = MBBI->getOperand(0).getReg(); in ExpandMI()
2326 AFI->isThumb1OnlyFunction()); in ExpandMI()
2341 if (AFI->isThumb2Function()) { in ExpandMI()
2342 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg) in ExpandMI()
2351 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg) in ExpandMI()
2355 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg) in ExpandMI()
2367 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr)) in ExpandMI()
2372 NewCall->addOperand(MO); in ExpandMI()
2374 MI.getMF()->moveCallSiteInfo(&MI, NewCall.getInstr()); in ExpandMI()
2378 CMSEPopCalleeSaves(*TII, MBB, MBBI, JumpReg, AFI->isThumb1OnlyFunction()); in ExpandMI()
2387 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), in ExpandMI()
2399 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; in ExpandMI()
2400 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), in ExpandMI()
2412 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2425 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), in ExpandMI()
2440 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI()
2441 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
2452 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; in ExpandMI()
2453 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), in ExpandMI()
2466 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; in ExpandMI()
2467 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), in ExpandMI()
2490 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
2502 MachineFunction &MF = *MI.getParent()->getParent(); in ExpandMI()
2505 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); in ExpandMI()
2510 int32_t NumBytes = AFI->getFramePtrSpillOffset(); in ExpandMI()
2512 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && in ExpandMI()
2515 if (AFI->isThumb2Function()) { in ExpandMI()
2517 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); in ExpandMI()
2518 } else if (AFI->isThumbFunction()) { in ExpandMI()
2520 FramePtr, -NumBytes, *TII, RI); in ExpandMI()
2523 FramePtr, -NumBytes, ARMCC::AL, 0, in ExpandMI()
2530 assert (!AFI->isThumb1OnlyFunction()); in ExpandMI()
2536 unsigned bicOpc = AFI->isThumbFunction() ? in ExpandMI()
2538 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) in ExpandMI()
2540 .addImm(MaxAlign.value() - 1) in ExpandMI()
2552 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2564 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2580 if (STI->genLongCalls()) { in ExpandMI()
2581 MachineConstantPool *MCP = MF->getConstantPool(); in ExpandMI()
2582 unsigned PCLabelID = AFI->createPICLabelUId(); in ExpandMI()
2584 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(), in ExpandMI()
2586 Register Reg = MI.getOperand(0).getReg(); in ExpandMI() local
2589 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) in ExpandMI()
2590 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4))); in ExpandMI()
2597 TII->get(Thumb ? gettBLXrOpcode(*MF) : getBLXOpcode(*MF))); in ExpandMI()
2600 MIB.addReg(Reg, RegState::Kill); in ExpandMI()
2603 TII->get(Thumb ? ARM::tBL : ARM::BL)); in ExpandMI()
2613 MF->moveCallSiteInfo(&MI, &*MIB); in ExpandMI()
2623 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg) in ExpandMI()
2628 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) in ExpandMI()
2661 // We need a new const-pool entry to load from. in ExpandMI()
2662 MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); in ExpandMI()
2671 ARMPCLabelIndex = AFI->createPICLabelUId(); in ExpandMI()
2679 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) in ExpandMI()
2680 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4))); in ExpandMI()
2687 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) in ExpandMI()
2703 unsigned LabelId = AFI->createPICLabelUId(); in ExpandMI()
2717 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg) in ExpandMI()
2722 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) in ExpandMI()
2729 TII->get(PICAddOpc)) in ExpandMI()
2755 if (MI.getMF()->getJumpTableInfo()->getEntryKind() == in ExpandMI()
2759 // Use a 32-bit immediate move to generate the address of the jump table. in ExpandMI()
2760 assert(STI->isThumb() && "Non-inline jump tables expected only in thumb"); in ExpandMI()
2765 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) in ExpandMI()
2778 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
2793 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); in ExpandMI()
2794 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI()
2798 // Add an implicit def for the super-register. in ExpandMI()
2809 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
2825 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); in ExpandMI()
2826 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI()
2831 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandMI()
3149 assert(STI->isThumb()); in ExpandMI()
3153 assert(STI->isThumb()); in ExpandMI()
3157 assert(STI->isThumb()); in ExpandMI()
3161 assert(!STI->isThumb()); in ExpandMI()
3165 assert(!STI->isThumb()); in ExpandMI()
3169 assert(!STI->isThumb()); in ExpandMI()
3178 Register Reg = MI.getOperand(0).getReg(); in ExpandMI() local
3179 assert(Reg == ARM::LR && "expect LR register!"); in ExpandMI()
3183 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) in ExpandMI()
3185 .addReg(Reg); in ExpandMI()
3188 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); in ExpandMI()
3191 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) in ExpandMI()
3195 .addReg(Reg); in ExpandMI()
3198 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); in ExpandMI()
3209 BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::tBL)); in ExpandMI()
3217 Bundler.append(BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::t2BTI))); in ExpandMI()
3228 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) in ExpandMI()
3229 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), in ExpandMI()
3231 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), in ExpandMI()
3258 TII = STI->getInstrInfo(); in runOnMachineFunction()
3259 TRI = STI->getRegisterInfo(); in runOnMachineFunction()
3275 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction